
Serial Interface with Time Slot Assigner
7-72
MC68360 USER’S MANUAL
Figure 7-26. Two TDMs with Dynamic Frames
7.8.4.5 PROGRAMMING SI RAM ENTRIES. The programming of each word within the
RAM determines the routing of the serial bits (or bit groups) and the assertion of strobe out-
puts. The RAM programming codes are as follows:
NOTES:
1: Only available on REV C mask or later. NOT Available on REV A or B.
Rev A mask is C63T
Rev B mask are C69T, and F35G
Current Rev C mask are E63C, E68C and F15W
Bit 15 LOOP (Loop back this time slot)
0 = normal mode
1 = loop back mode for this time slot
SWTR—Switch Tx and Rx
The SWTR bit is only valid in the receive route RAM and is ignored in the transmit route
RAM. This bit affects the operation of both the L1RXD and L1TXD pins
The SWTR bit would only be set in a special situation where the user desires to receive
data from a transmit pin and transmit data on a receive pin. For instance, consider the sit-
uation where devices A and B are connected to the same TDM, each with different time
slots. Normally, there is no opportunity for stations A and B to communicate with each oth-
er directly over the TDM, since they both receive the same TDM receive data and transmit
on the same TDM transmit signal (see Figure 7-27).
15
14
13
12
11
10
9876543210
LOOP1
SWTR
SSEL1–SSEL4
—
CSEL
CNT
BYT
LST
TWO CHANNELS WITH SHADOW RAM
FOR DYNAMIC ROUTE CHANGE
RDM = 11
16 ENTRIES
RXa
ROUTE
FRAMING SIGNALS
L1RSYNCa
SI RAM ADDRESS: 0
(16-BITS WIDE)
30
158
128
160
32
62
190
16 ENTRIES
RXb
ROUTE
FRAMING SIGNALS
L1RCLKb
L1RSYNCb
94
222
192
L1TCLKb
L1TSYNCb
224
96
126
254
64
16 ENTRIES
TXa
ROUTE
16 ENTRIES
TXb
ROUTE
16 ENTRIES
RXa
ROUTE
16 ENTRIES
RXb
ROUTE
16 ENTRIES
TXa
ROUTE
16 ENTRIES
TXb
ROUTE
L1RCLKa
L1TCLKa
L1TSYNCa
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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