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System Integration Module (SIM60)
6-36
MC68360 USER’S MANUAL
SWE—Software Watchdog Enable
This bit should be cleared by software after a system reset to disable the SWT. See
0 = SWT is disabled.
1 = SWT is enabled. (This is the default value after system reset.)
SWRI—Software Watchdog Reset/Interrupt Select
0 = SWT causes a level 7 interrupt to the CPU32+.
1 = SWT causes a system reset. (This is the default value after system reset.)
NOTE
For more information on reset see 4.7 Reset Operation.
SWT1–SWT0—Software Watchdog Timing
These bits, along with the SWP bit in the PITR, control the divide ratio used to establish
the timeout period for the SWT. The default value (11) yields the maximum timeout period.
The SWT timeout period is given by the following formula:
or
The SWT timeout period listed in
Table 6-4 gives the formula to derive the SWT timeout for
any clock frequency. The timeout periods are listed for various input frequencies. Note that
the input frequency to the SWT is called EXTALDIV in the formulas and is the EXTAL fre-
quency divided by 1 or by 128, depending on the MODCK1–MODCK0 pins.
NOTES:
1. Note that a 4.192-MHz oscillator produces the same 32.768 input frequency (the 4.192 MHz is divided by 128 in the
oscillator circuit).
2. Programming for this timeout period must be done after the programming of the PLL. See also
6.9.3.10 PLL Control1
(EXTALDIV)/(divide count)
divide count
EXTALDIV
Table 6-4. Deriving SWT Timeout
SWP
SWT1–SWT0
Software Timeout Period
32.768 kHz1
16.677 MHz
25 MHz
33.354 MHz
000
29/Input frequency2
15.6 ms
3.9 ms
2.6 ms
1.9 ms
001
211/Input frequency
62.5 ms
15.7 ms
10.5 ms
7.9 ms
010
213/Input frequency
250 ms
62.9 ms
41.9 ms
31.4 ms
011
215/Input frequency
1 s
251.5 ms
167.7 ms
125.7 ms
100
218/Input frequency
8 s
2.0 s
1.3 s
1.0 s
101
220/Input frequency
32 s
8.0 s
5.4 s
4.0 s
110
222/Input frequency
128 s
32.2 s
21.5 s
16.1 s
111
224/Input frequency
512 s
128.8 s
85.9 s
64.4 s
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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