
Parallel Interface Port (PIP)
MC68360 USER’S MANUAL
Supports Closed Loop Handshake for Higher Data Transfer Rates
Supports Centronics Transmitter and Receiver Operating Modes
Supports Bidirectional Centronics (P1284)
Flexible Message-Oriented Data Structure
Flexible Control Character Comparison (Receiver)
Flexible Timing Modes
Programmable timing parameters
7.13.8.2 CENTRONICS CHANNEL TRANSMISSION. The Centronics transmitter supports
the same general data structure that is used by the SCCs for other protocols. When the STR
bit in the PIP configuration register is set, the Centronics controller will process the next
buffer descriptor (BD) in the Centronics transmitter BD table. If the BD is ready, the Centron-
ics transmitter will fetch the data from the memory and start sending it to the printer. If the
status mask bits are set in the SMASK register, the printer status line (Select, PError and
Fault) will be checked before each transfer. In this case, the user should configure PB1,2,3
pins as general purpose inputs and connect them to Select, PError, and Fault respectively.
For each transfer the Centronics controller will output the data on the Centronics interface
data lines and will generate the strobe pulse if previous data was acknowledged and the
minimum setup time was met. The strobe pulse width and the setup time parameters are
programmed by the PIP Timing Parameter Register (PTPR). A single data frame may span
several BDs. A maskable interrupt can be generated after the processing of each BD.
7.13.8.3 CENTRONICS TRANSMITTER MEMORY MAP. When configured to operate in
Centronics Transmit mode, the QUICC overlays the structure illustrated in Table 7-17 with
the SMC2 parameter RAM area.
Table 7-17. Centronics Transmitter Parameter RAM
Address
Name
Width
Description
PIP Base+00
Res
Word
Reserved
PIP Base+02
TBASE
Word
Tx Buffer Descriptors Base Address
PIP Base+04
CFCR
Byte
Centronics Function Code
PIP Base+05
SMASK
Byte
Status Mask
PIP Base+06
Res
Word
Reserved
PIP Base+08
Res
Long
Reserved
PIP Base+0C
Res
Long
Reserved
PIP Base+10
Res
Word
Reserved
PIP Base+12
Res
Word
Reserved
PIP Base+14
Res
Long
Reserved
PIP Base+18
TSTATE
Long
Tx Internal State
PIP Base+1C
T_PTR
Long
Tx Internal Data Pointer
PIP Base+20
TBPTR
Word
Tx Buffer Descriptor Pointer
PIP Base+22
T_CNT
Word
Tx Internal Byte Count
PIP Base+24
TTEMP
Long
Tx Temp
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.