參數(shù)資料
型號： KBE00G003M
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： NAND 512Mb*2 + Mobile SDRAM 256Mb*2
中文描述： NAND閃存的512Mb * 2移動SDRAM 256Mb的* 2
文件頁數(shù)： 56/89頁
文件大?。?/td> 1238K
代理商： KBE00G003M
KBE00G003M-D411
MCP MEMORY
July 2005
56
Revision 0.1
D. DEVICE OPERATIONS
BANK ADDRESSES (BA0 ~ BA1)
: In case x 16
This SDRAM is organized as four independent banks of
4,194,304 words x 16 bits memory arrays. The BA0 ~ BA1 inputs
are latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA0 ~
BA1 are latched at bank active, read, write, mode register set
and precharge operations.
: In case x 32
This SDRAM is organized as four independent banks of
2,097,152 words x 32 bits memory arrays. The BA0 ~ BA1 inputs
are latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA0 ~
BA1 are latched at bank active, read, write, mode register set
and precharge operations.
ADDRESS INPUTS (A0 ~ A12)
: In case x 16
The 22 address bits are required to decode the 4,194,304 word
locations are multiplexed into 13 address input pins (A0 ~ A12).
The 13 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 9 bit column addresses
are latched along with CAS, WE and BA0 ~ BA1 during read or
write command.
: In case x 32
The 21 address bits are required to decode the 2,097,152 word
locations are multiplexed into 12 address input pins (A0 ~ A11).
The 12 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 9 bit column addresses
are latched along with CAS, WE and BA0 ~ BA1 during read or
write command.
BANK ADDRESSES (BA0 ~ BA1)
: In case x 16
This SDRAM is organized as four independent banks of
8,388,608 words x 16 bits memory arrays. The BA0 ~ BA1 inputs
are latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA0 ~
BA1 are latched at bank active, read, write, mode register set
and precharge operations.
: In case x 32
This SDRAM is organized as four independent banks of
4,194,304 words x 32 bits memory arrays. The BA0 ~ BA1 inputs
are latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA0 ~
BA1 are latched at bank active, read, write, mode register set
and precharge operations.
ADDRESS INPUTS (A0 ~ A12)
: In case x 16
The 23 address bits are required to decode the 8,388,608 word
locations are multiplexed into 13 address input pins (A0 ~ A12).
The 13 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 10 bit column
addresses are latched along with CAS, WE and BA0 ~ BA1 dur-
ing read or write command.
: In case x 32
The 22 address bits are required to decode the 8,388,608 word
locations are multiplexed into 13 address input pins (A0 ~ A12).
The 13 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 9 bit column addresses
are latched along with CAS, WE and BA0 ~ BA1 during read or
write command.
ADDRESSES of 256Mb
ADDRESSES of 512Mb
相關(guān)PDF資料
PDF描述
KBE00G003M-D411 NAND 512Mb*2 + Mobile SDRAM 256Mb*2
KBE00S009M 1Gb NAND x 2 + 256Mb Mobile SDRAM x 2
KBE00S009M-D411 1Gb NAND x 2 + 256Mb Mobile SDRAM x 2
KBJ2501 25A SINGLE PHASE SILICON BRIDGE RECTIFIER
KBJ2502 25A SINGLE PHASE SILICON BRIDGE RECTIFIER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KBE00G003M-D411 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:NAND 512Mb*2 + Mobile SDRAM 256Mb*2
KBE00S003M 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb NAND*2 + 256Mb Mobile SDRAM*2
KBE00S003M-D411 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb NAND*2 + 256Mb Mobile SDRAM*2
KBE00S009M 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb NAND x 2 + 256Mb Mobile SDRAM x 2
KBE00S009M-D411 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb NAND x 2 + 256Mb Mobile SDRAM x 2
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