參數(shù)資料
型號(hào)： HSP50216KI
廠商： HARRIS SEMICONDUCTOR
元件分類： 無(wú)繩電話/電話
英文描述： Four-Channel Programmable Digital DownConverter
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196
封裝： BGA-196
文件頁(yè)數(shù)： 6/53頁(yè)
文件大?。?/td> 561K
代理商： HSP50216KI
6
The HSP50216 is programmed through a 16-bit
microprocessor interface. The output data can also be read
via the microprocessor interface for all channels that are
synchronized. The HSP50216 is specified to operate to a
maximum clock rate of 70MSPS over the industrial
temperature range (-40
o
C to 85
o
C). The power supply
voltage range is 3.3V
±
0.15V. The I/Os
are not
5V tolerant.
Input Select/Format Block
Each front end block and the level detector block contains an
input select/format block. A functional block diagram is
provided in the above figure. The input source can be any of
the four parallel input busses (see Microprocessor Interface
Section Table 1, IWA *000h) or a test register loaded via the
processor bus (see Microprocessor Interface Section Table
40, GWA F807h).
The input to the part can operate in a gated or interpolated
mode. Each input channel has an input enable (ENIx, x = A,
B, C or D). In the gated mode, one input sample is
processed per clock that the ENIx signal is asserted (low).
Processing is disabled when ENIx is high. The ENIx signal is
pipelined through the part to minimize delay (latency). In the
interpolated mode, the input is zeroed when the ENIx signal
is high, but processing inside the part continues. This mode
inserts zeros between the data samples, interpolating the
input data stream up to the clock rate. On reset, the part is
set to gated mode and the input enables are disabled. The
inputs are enabled by the first SYNCI signal.
The input section can select one channel from a multiplexed
data stream of up to 8 channels. The input enable is delayed
by 0 to 7 clock cycles to enable a selection register. The
register following the selection register is enabled by the
non-delayed input enable to realign the processing of the
channels. The one-clock-wide input enable must align with
the data for the first channel. The desired channel is then
selected by programming the delay. A delay of zero selects
the first channel, a delay of 1 selects the second, etc.
The parallel input busses are 16 bits wide. The input format
may be twos complement or offset binary format. A floating
point mode is also supported. The floating point modes and
the mapping of the parallel 16-bit input format is discussed
below.
Floating Point Input Mode Bit Mapping
The input bit weighting for fixed point is 2
0
(corresponding to
parallel input bus A, B, C or D bit 15) to 2
-15
(corresponding
to parallel input bus A, B, C or D bit 0). For floating point
modes, the least significant 2 or 3 bits are used as exponent
bits (See Floating Point Input Mode Bit Mapping Tables). The
difference between the four floating point modes with three
exponent bits is where the exponent saturates.
HSP50216
相關(guān)PDF資料
PDF描述
HSP50307SC Burst QPSK Modulator
HSP50307EVAL1 2.0GHz to 2.7GHz DownConverter
HSP50415 Wideband Programmable Modulator(寬帶可編程調(diào)制器)
HSR312 PHOTOVOLTAIC SOLID-STATE RELAY OPTOCOUPLERS
HSR312L PHOTOVOLTAIC SOLID-STATE RELAY OPTOCOUPLERS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HSP50216KIZ 功能描述:上下轉(zhuǎn)換器 MULTI-CH PROGRAM CONV BGA PKG IND RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
HSP50306 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital QPSK Demodulator
HSP50306 WAF 制造商:Intersil Corporation 功能描述:
HSP50306_04 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital QPSK Demodulator
HSP50306SC-25 制造商:Rochester Electronics LLC 功能描述:- Bulk
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*