參數(shù)資料
型號(hào)： HSP50216KI
廠商： HARRIS SEMICONDUCTOR
元件分類： 無繩電話/電話
英文描述： Four-Channel Programmable Digital DownConverter
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196
封裝： BGA-196
文件頁(yè)數(shù)： 25/53頁(yè)
文件大小： 561K
代理商： HSP50216KI
25
(external) addresses ADD(2:0) = 0 and 1 (bits 15:0 at
address 0 and 31:16 at address 1). The data types available
via the indirect read are listed in the Tables of Indirect Read
Address (IRA) Registers. (Note that the
μ
PHold bit
contained in the target register at Indirect Write Address
(IWA) = *00Ah must be set to suspend the filter compute
engine before the memories can be written to or read from.)
The HSP50216 output data from the four channels is
available through the microprocessor interface as well as
from the serial data outputs. A FIFO-like interface is used to
read the output data through the microprocessor interface.
When new output data is available, it is loaded into a FIFO in
a user programmed order (for details on the programming
order see Global Write Address (GWA) = F820h - F83Fh). It
can then be read, 16 bits at a time, at direct address 2,
ADD(2:0) = 2. At the end of each read, the FIFO counter is
advanced to the next location. This allows a DMA controller
to read all of the data with successive reads to a single direct
address. No writes or other interaction is required. The FIFO
counter is reset and reloaded by each interrupt signal, see
GWA F802h. New data in the FIFO is also indicated in the
status register located at direct address ADD(2:0) = 3 if a
polled mode is preferred. The eight data types available, for
each of the four channels, via this interface are: I(23:8),
I(7:0)+8 Zeroes, Q(23:8), Q(7:0)+8 Zeroes, Mag(23:8),
Mag(7:0)+8 Zeroes, Phase (15:0), and AGC (15:0). The
upper bits of I, i.e., I(23:8), and Q, i.e., Q(23:8), are not
rounded to 16 bits. This interface can read the data from all
the channels that are synchronized. However, because a
common FIFO is used and the FIFO is reset and reloaded by
each interrupt, it cannot be used for asynchronous channels.
The direct address map for the microprocessor interface is
shown in the Table of Microprocessor Direct Read/Write
Addresses and the procedures for reading and writing to this
interface are provided below. The bit field details for each
indirect read and write address is provided in the Table of
Indirect Read Address (IRA) Registers, Tables of Indirect
Write Address (IWA) Registers (Tables 1 - 32) and Tables of
Global Write Address (GWA) Registers (Tables 33 - 43).
μ
P Read/Write Procedures
To Write to the Internal Registers:
1. Load the indirect write holding registers at direct address
ADD(2:0) = 0 and 1 with the data for the internal register
(16 or 32 bits depending on the internal register being
addressed).
2. Write the Indirect Write Address of the internal register
being addressed to direct address ADD(2:0) = 2 (Note: A
write strobe to transfer the contents of the Indirect Write
Holding Register into the Target Register specified by the
Indirect Address will be generated internally).
3. Wait4clockcyclesbeforeperformingthenextwritetothe
indirect write holding registers.
To Write to the Internal Instruction/Coefficient
RAMs:
1. Put the filter compute engine of the desired channel into
the hold mode by setting bit 31 of the Filter Compute
Engine / Resampler Control register located at
IWA = *00Ah (Note: The * is equal to 0, 1, 2 or 3
depending on the channel being addressed). By setting
bit31allFIRprocessingforthechanneladdressedwillbe
stopped.
2. Load the indirect write holding registers at direct address
ADD(2:0) = 0 and 1 with the data for the internal RAM
location.
3. Write the Indirect Write Address of the internal RAM
location being addressed to direct address ADD(2:0) = 2
(Note: A write strobe to transfer the contents of the
Indirect Write Holding Register into the RAM location
specified by the Indirect Address will be generated
internally).
4. Wait4clockcyclesbeforeperformingthenextwritetothe
indirect write holding registers.
5. After all data has been loaded, set the
μ
PHold bit back
low.
To Read Internal Registers:
1. Write the Indirect Read Address of the internal register
being addressed to direct address ADD(2:0) = 3.
2. Perform a read of the Indirect Read Holding Registers at
direct address ADD(2:0) = 0 and 1.
To Read Data Outputs:
1. Setupthe
μ
PFIFOReadOrderControlRegister(located
at Global Write Address (GWA) = F820h - F83Fh).
2. Wait for interrupt or check flag.
3. Data can then be read, 16 bits at a time, at direct
address 2, ADD(2:0) = 2.
4. Repeat step 3 for desired number of words.
5. Go to step 2.
To Read Instruction/Coefficient Values:
1. Put the filter compute engine of the desired channel into
the hold mode by setting bit 31 of the Filter Compute
Engine / Resampler Control register located at
IWA = *00Ah (Note: The * is equal to 0, 1, 2 or 3
depending on the channel being addressed).
2. Write the Indirect Read Address (IRA) of the internal
RAM/ROM location being addressed to direct address
ADD(2:0) = 3.
3. Wait 4 clock cycles.
4. Read the data at direct address ADD(2:0) = 0 and 1.
5. After all the data has been read, set the
μ
PHold bit back
low.
HSP50216
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