參數(shù)資料
型號: HSP50216KI
廠商: HARRIS SEMICONDUCTOR
元件分類: 無繩電話/電話
英文描述: Four-Channel Programmable Digital DownConverter
中文描述: TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196
封裝: BGA-196
文件頁數(shù): 13/53頁
文件大?。?/td> 561K
代理商: HSP50216KI
13
multiplexed together to get the desired 8.192MSPS. The
input sample rate to the final filter of each channel must
meet Nyquist for the final output to assure that no
information is lost due to aliasing.
The number of FIR taps available for these requirements is
calculated as follows:
65536/2048 = 32 clocks
minus (8writes + 1wait + 1jump = 10clocks)
= 22 clocks
Therefore, the number of taps is:
22 x 2 = 44 taps.
Multiplexing the four outputs gives a final output sample rate
of 8.192.
The impulse response is 44 taps at 16.384M or 22 output
samples (11 symbols at 4.096M).
The AGC loop filter output of channel 4 can be routed to
control the forward AGC gain control of all four channels.
This assures that the gains of the four back end sections are
the same. The gain error, however, is only computed from
every fourth output sample.
The back end processing sections of two or more HSP50216s
can be combined using the same polyphase approach, but
the AGC gain from one part cannot be shared with another
part (except via the
μ
P interface), so polyphase filter using
multiple parts would typically usually use a fixed gain.
Filter Sequencer
SAMPLE FILTER #4 PROGRAM
STEP
INSTRUCTION
0
Wait for enough input samples (8 in this case)
1
FIR
type = even symmetry
44 taps
decx8
compute one output
memory block size 64
memory block start at 0
coefficient block start at 64
step size 1
output to AGC
offset memory read pointers by 0, -2, -4, -6
2
Jump, Unconditional, to 0
HSP50216
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