參數(shù)資料
型號： HSP50216KI
廠商： HARRIS SEMICONDUCTOR
元件分類： 無繩電話/電話
英文描述： Four-Channel Programmable Digital DownConverter
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196
封裝： BGA-196
文件頁數(shù)： 39/53頁
文件大?。?/td> 561K
代理商： HSP50216KI
39
2:0
SCLK rate.
000
001
010
011
100
101
Other codes are undefined.
Serial clock disabled.
Serial clock rate is Input CLK Rate.
Serial clock rate is Input CLK Rate/2.
Serial clock rate is Input CLK Rate/4.
Serial clock rate is Input CLK Rate/8.
Serial clock rate is Input CLK Rate/16.
TABLE 36. SERIAL CLOCK CONTROL REGISTER (GWA = F803h) (Continued)
P(15:0)
FUNCTION
TABLE 37. INPUT LEVEL DETECTOR SOURCE SELECT/FORMAT REGISTER (GWA = F804h)
P(15:0)
FUNCTION
15:13
Channel Input Source Selection. Selects as the data input for the level detector either A(15:0), B(15:0), C(15:0), D(15:0) or the
μ
P
Test Input register as shown below.
15:13
000
001
010
011
100
Source Selected
A(15:0)
B(15:0)
C(15:0)
D(15:0)
μ
P Test input register.
This is provided for testing and to zero the input data bus when a channel is not in use.
The Top Level Control register address for the
μ
P Test input register is F807h.
12
μ
P Register input enable select
1 = bit 11, 0 = one clock wide pulse on each write to location F808h. Select 0 to write data test data into the part. Select 1 to input a
constant or to disable the input for minimum power dissipation when an NCO/mixer/CIC section is unused.
11
μ
P input enable. When bit 12 is set, this bit is the input enable for the
μ
P register input. Active low. 0=enabled, 1=disabled.
10
Parallel Data Input Format
0
Two’s complement
1
Offset binary
9
Fixed/Floating point
0
Fixed point
1
Floating point. The 16-bit input bus is divided into mantissa and exponent bits grouped either 13/3 or 14/2 depending on bits
8 and 7. See text.
8:7
Floating point mantissa size select. The 16-bit data input is grouped as a 13/3 or 14/2 mantissa/exponent word. These control bits
select the mantissa/exponent grouping, add an offset to the exponent and set the shift control saturation level.
00
11/3 bits 15:5 mantissa, 2:0 exponent
01
12/3 bits 15:4 mantissa, 2:0 exponent
10
13/3 bits 15:3 mantissa, 2:0 exponent
11
14/2 bits 15:2 mantissa, 1:0 exponent
6:4
De-multiplex control. These control bits are provided to demultiplex an input data stream comprised of a set of multiplexed data
streams. Up to 8 multiplexed data streams can be demultiplexed. These control bits select how many clocks after the ENIx signal to
wait before taking the input sample. ENIx should be asserted for one clock period and aligned with the first channel of the multiplexed
data set. For example, if four streams are multiplexed at half the clock rate, ENIx would align with the first clock period of the first
stream, the second would start two clocks later, the next 4 clocks after ENIx, etc. The samples are aligned with ENIx (zero delay) at
the input of the NCO/Mixer/CIC stage at the next ENIx.
000
zero delay
111
7 clock periods of delay.
HSP50216
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