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參數(shù)資料
| 型號： | HSP50216KI |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Four-Channel Programmable Digital DownConverter |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196 |
| 封裝： | BGA-196 |
| 文件頁數(shù)： | 23/53頁 |
| 文件大?。?/td> | 561K |
| 代理商： | HSP50216KI |
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23
Serial Data Output Formatter Section
Serial Data Output Control Register
The serial data output control register contains sync position
and polarity (SYNCA, B, C or D), channel multiplexing, and
scaling controls for the SD1x and SD2x (x = A, B, C or D)
serial outputs (see Microprocessor Interface Section, Table
21, IWA *014h).
Channel Routing Mask
The multiplexing mask bits for each channel (see
Microprocessor Interface Section Table 21, IWA *014h bits
19:16 for SD1x or bits 15:12 for SD2x) can be used to enable
that channel’s output to any of the four serial outputs. These
bits control the AND gates that mask off the channels, so a
zero disables the channel’s connection to that output.
To configure more than one channel's output onto a serial
data output, the SD1 serial outputs and syncs from each
channel (0,1, 2 and 3) are brought to each of the SD1 serial
output sections and the SD2 serial outputs are brought to
each of the SD2 serial output sections (the syncs are only
associated with the SD1 serial ouputs). There, the four
outputs are AND-ed with the multiplexing mask programmed
in the serial data output control registers of channels 0 thru 3
and OR-ed together. By gating off the channels that are not
wanted and delaying the data from each desired channel
appropriately, the channels can be multiplexed into a
common serial output stream. It should be noted that in
order to multiplex multiple channels onto a single serial data
stream the channels to be multplexed must be synchronous.
Serial Data Output Time Slot Content/Format
Registers
These four registers are used to program the content and
format of the serial data output sequence time slots (see
Microprocessor Interface Section, Tables 22 - 25,
IWA *015h - *018h). There are seven data time slots that
make up a serial data output stream. The number of data
bits and data format of each slot is programmable as well as
whether there will be a sync generated with the time slot (the
syncs are only associated with the SD1 serial ouputs). Any
of seven types of data or zeros can be chosen for each time
slot. Eight bits are used to specify the content and format of
each slot.
As an example, suppose we wanted to output 32-bit I and Q
values from channels 0 and 1 into the SD1A serial data
output stream, we would program the following settings in
the channel’s serial data output control and content/format
registers:
Channel 0:
delay = 0 (IWA = 0014h, bits 11:0);
HSP50216
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50216KIZ | 功能描述:上下轉(zhuǎn)換器 MULTI-CH PROGRAM CONV BGA PKG IND RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50306 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital QPSK Demodulator |
| HSP50306 WAF | 制造商:Intersil Corporation 功能描述: |
| HSP50306_04 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital QPSK Demodulator |
| HSP50306SC-25 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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