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參數(shù)資料
| 型號： | HSP50216KI |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Four-Channel Programmable Digital DownConverter |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196 |
| 封裝： | BGA-196 |
| 文件頁數(shù)： | 14/53頁 |
| 文件大?。?/td> | 561K |
| 代理商： | HSP50216KI |
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14
The filter sequencer is programmed via an instruction RAM
and several control registers. These are described below.
Instruction RAMs
The filter compute engine is controlled by a simple
sequencer supporting up to 32 steps. Each step can be a
filter or one of four sequence flow instructions - wait, jump
(conditional or unconditional), load loop counter, or NOP.
There are 128 bits per instruction word with each word
consisting of condition code selects, FIR parameters and
data routing controls. Not all of the instruction word bits are
used for all instruction types. The actual sequencer
instruction is only 9 bits. The rest of the bits are used for filter
parameters or for the loop counter preload. Each sequence
step is loaded in four 32-bit writes. The mapping of the bit
fields for the instruction types is shown in the instruction bit
field table that follows.
When the filter is reset, the instruction pointer is set to 31
(the last instruction step). The read and write pointers are
initialized on reset, so a reset must be done when the
channel is initialized or restarted.
A fixed offset can be added to the starting read address of
the filter in one sequence step. This function is provided to
offset the data reads of the filters in a polyphase filter bank -
all filters in the bank will write the same data to the same
RAM location. To offset the computations the RAM read
address is offset.
The instruction word bits (127:0) are assigned to memory
words as follows:
31:0 to destination C C C C 0 0 0 1 0 x x x x x 0 0
63:32 to destination C C C C 0 0 0 1 0 x x x x x 0 1
95:64 to destination C C C C 0 0 0 1 0 x x x x x 1 0
127:96 to destination C C C C 0 0 0 1 0 x x x x x 1 1
where CCCC is the channel number and xxxxx is the
instruction sequence step number. Note the
μ
PHold bit in
the filter compute engine control register (IWA = *00Ah)
must be set for the microprocessor to read from or write to
the instruction or coefficient RAMs.
HSP50216
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| HSP50307EVAL1 | 2.0GHz to 2.7GHz DownConverter |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50216KIZ | 功能描述:上下轉換器 MULTI-CH PROGRAM CONV BGA PKG IND RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50306 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital QPSK Demodulator |
| HSP50306 WAF | 制造商:Intersil Corporation 功能描述: |
| HSP50306_04 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital QPSK Demodulator |
| HSP50306SC-25 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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