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參數(shù)資料
| 型號： | HSP50216KI |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Four-Channel Programmable Digital DownConverter |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196 |
| 封裝： | BGA-196 |
| 文件頁數(shù)： | 31/53頁 |
| 文件大?。?/td> | 561K |
| 代理商： | HSP50216KI |
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31
TABLE 13. WAIT THRESHOLD/DECREMENT VALUE REGISTER (IWA = *00Ch)
P(15:0)
FUNCTION
31
μ
PTestBit. This bit is provided as a microprocessor controlled condition code for the filter compute engine for conditional execution
or synchronous startup. Active high.
30
Set to 0.
29:20
Decrement value 1. Positive number.
19:10
Decrement value 0. Positive number. Usually set equal to the Threshold (bits 9:0).
9:0
Threshold. Number of samples needed to run a filter set and produce an output.
TABLE 14. RESET WRITE POINTER OFFSET REGISTER (IWA = *00Dh)
P(15:0)
FUNCTION
8:0
This parameter is the offset between filter compute engine read and write pointers on filter compute engine reset. On reset, the read
and write pointers for all the filters are loaded, the read pointer with zero and the write pointer with this value. Set to zero for a single
filter and two for a multi-filter chain.
TABLE 15. AGC GAIN LOAD REGISTER (IWA = *00Eh)
P(15:0)
FUNCTION
15:0
This location loads the AGC accumulator. If the loop attack/decay gain is set to zero and this value is within the AGC gain limits, the
AGC will hold this value. If not, the AGC will be set to this gain (or to a limit) and then start to settle.
4xE (15:12), 12xM, (11:0)
TABLE 16. AGC GAIN READ STROBE REGISTER (IWA = *00Fh)
P(15:0)
FUNCTION
31:0
for RD;
N/A for WR
Writing to this location will sample the AGC loop filter output (forward gain value) to stabilize it for reading. The value is read from
this location after waiting the 4 clocks required for read synchronization.
31:16
15:0
AGC Gain for Channel 1.
AGC Gain for Channel 0.
TABLE 17. AGC LOOP ATTACK/DECAY GAIN VALUES REGISTER (IWA = *010h)
P(15:0)
FUNCTION
31:24
Loop gain 0, decay gain value (signal decay, increase gain) 31:28 = EEEE (exponent), 27:24 = MMMM (mantissa)
23:16
Loop gain 1, decay gain value 23:20 = EEEE (exponent), 19:16 = MMMM (mantissa)
15:8
Loop gain 0, attack gain value (signal arrival, decrease gain) 15:12 = EEEE (exponent), 11:8 = MMMM (mantissa)
7:0
Loop gain 1, attack gain value 7:4 = EEEE (exponent), 3:0 = MMMM (mantissa)
TABLE 18. AGC GAIN LIMITS REGISTER (IWA = *011h)
P(15:0)
FUNCTION
31:16
Upper gain limit. See AGC section.
15:0
Lower gain limit. See AGC section.
TABLE 19. AGC THRESHOLD REGISTER (IWA = *012h)
P(15:0)
FUNCTION
15:0
AGC threshold. Equals 1.64676 times the desired magnitude of the I1/Q1 output.
HSP50216
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50216KIZ | 功能描述:上下轉(zhuǎn)換器 MULTI-CH PROGRAM CONV BGA PKG IND RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50306 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital QPSK Demodulator |
| HSP50306 WAF | 制造商:Intersil Corporation 功能描述: |
| HSP50306_04 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital QPSK Demodulator |
| HSP50306SC-25 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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