參數(shù)資料
型號(hào)： HSP50216KI
廠商： HARRIS SEMICONDUCTOR
元件分類： 無(wú)繩電話/電話
英文描述： Four-Channel Programmable Digital DownConverter
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196
封裝： BGA-196
文件頁(yè)數(shù)： 36/53頁(yè)
文件大?。?/td> 561K
代理商： HSP50216KI
36
TABLE 29. FILTER COMPUTE ENGINE INSTRUCTION RAMS (IWA = *100h THRU *17Fh)
P(15:0)
FUNCTION
31:0
These locations in RAM are used to store the Filter Compute Engine instruction words. There are 128 bits per instruction word with
each word consisting of condition code selects, FIR parameters and data routing controls. The filter compute engine is controlled by
a simple sequencer supporting up to 32 steps where each step is defined by a 128 bit instruction word. The 128 bit instruction word
is assigned to RAM memory in four 32 bit data writes through the Microprocessor Interface. Hence, 128 32-bit memory locations are
required per channel to support the 32 steps of the Filter Sequencer. See the Filter Compute Engine and Filter Sequencer sections
of the data sheet for more details.
TABLE 30. FILTER COMPUTE ENGINE INSTRUCTION POINTER RAMS (IWA = *180h THRU *1FCh)
P(15:0)
FUNCTION
TABLE 31. FILTER COMPUTE ENGINE COEFFICIENT RAM1 (IWA = *440h THRU *47Fh)
P(15:0)
FUNCTION
31:0
These locations in RAM are used to store the 22-bit filter coefficients used by the Filter Compute Engine of each channel in
implementing a FIR filter. The 22-bit FIR filter coefficients are loaded in the upper 22 bits of each 32-bit RAM location. The two LSBs
of the second byte (bits 9:8 of the total 32 bits, 31:0) are the shift bits. These are set to zero if not used. The least significant byte
(bits 7:0 of the total 32 bits, 31:0) are ignored. RAM1 address space allows for storage of 64 filter coefficients out of the total of 192
filter coefficient storage locations. See the Filter Compute Engine and Filter Sequencer sections of the data sheet for more details.
TABLE 32. FILTER COMPUTE ENGINE COEFFICIENT RAM2 (IWA = *480h THRU *4FFh)
P(15:0)
FUNCTION
31:0
These locations in RAM are used to store the 22-bit filter coefficients used by the Filter Compute Engine of each channel in
implementing a FIR filter. The 22-bit FIR filter coefficients are loaded in the upper 22 bits of each 32-bit RAM location. The two LSBs
of the second byte (bits 9:8 of the total 32 bits, 31:0) are the shift bits. These are set to zero if not used. The least significant byte
(bits 7:0 of the total 32 bits, 31:0) are ignored. RAM1 address space allows for storage of 128 filter coefficients out of the total of 192
filter coefficient storage locations. See the Filter Compute Engine and Filter Sequencer sections of the data sheet for more details.
HSP50216
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