參數(shù)資料
型號： HSP50216KI
廠商： HARRIS SEMICONDUCTOR
元件分類： 無繩電話/電話
英文描述： Four-Channel Programmable Digital DownConverter
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196
封裝： BGA-196
文件頁數(shù)： 43/53頁
文件大?。?/td> 561K
代理商： HSP50216KI
43
AC Test Load Circuit
MICROPROCESSOR WRITE TIMING
P(15:0) Setup Time to Rising Edge of WR
t
DSW
10
-
ns
P(15:0) Hold Time from Rising Edge of WR
t
DHW
-2
-
ns
A(1:0) Setup Time to Rising Edge of WR
t
ASW
10
-
ns
A(1:0) Hold Time from Rising Edge of WR
t
AHW
-2
-
ns
CE Setup Time to Rising Edge of WR
t
CSW
10
-
ns
CE Hold Time from Rising Edge of WR
t
CHW
-2
-
ns
WR Low Time
t
WL
5
-
ns
MICROPROCESSOR READ TIMING
A(1:0) Setup Time to FALLING Edge of RD
t
ASR
8
-
ns
A(1:0) Hold Time from RISING Edge of RD
t
AHR
-2
-
ns
RD Enable Time
t
RE
-
11.5
ns
RD Disable Time (Note 9)
t
RD
-
8
ns
RD to P(15:0) Data Valid Time
t
DV
-
12
ns
CE Setup Time to Falling Edge of RD
t
CSR
8
-
ns
CE Hold Time from Rising Edge of RD
t
CHR
-2
-
ns
SERIAL CLOCK OUTPUT TIMING
CLK to Serial Data, Sync and SCLK (Divide-by 2 thru 16 Modes)
t
PD
-
6.5
ns
CLK Low to SCLK Low (Divide-by 1 Mode, Note 9)
t
PDL
-
6.5
ns
CLK High to SCLK High (Divide-by 1 Mode, Note 9)
t
PDH
-
3
ns
Time Skew Between SCLK and Serial Data or Serial Sync (Divide-by 2 thru 16 Modes, Note 9)
t
SKEW1
-1
1
ns
Time Skew Between SCLK and Serial Data or Serial Sync (Divide-by 1 Mode, Note 9)
t
SKEW2
0.5
2
ns
NOTES:
8. The HSP50216 goes into reset immediately on RESET going low and comes out of reset on the 4th rising edge of CLK after RESET goes high.
9. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes.
AC Electrical Specifications
V
CC
= 3.3V
±
0.15V, T
A
= -40
o
C to 85
o
C Industrial
(Continued)
PARAMETER
SYMBOL
MIN
MAX
UNITS
EQUIVALENT CIRCUIT
C
L
(NOTE)
I
OH
1.5V
I
OL
DUT
SWITCH S1 OPEN FOR I
CCSB
AND I
CCOP
S
1
±
NOTE - TEST HEAD CAPACITANCE, 40pF (TYP)
HSP50216
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