參數(shù)資料
型號(hào)： HSP50216KI
廠商： HARRIS SEMICONDUCTOR
元件分類： 無(wú)繩電話/電話
英文描述： Four-Channel Programmable Digital DownConverter
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196
封裝： BGA-196
文件頁(yè)數(shù)： 16/53頁(yè)
文件大?。?/td> 561K
代理商： HSP50216KI
16
28:18
Destination
Destination Field Bit Mapping
28
27
AGCLFGN AGCLF Path1 Path0 OS
AGCLFGNAGC loop gain select. Only applies to Path 1.
Loop gain 0 or 1 if AGCLF bit is set. Set to 0 (1 is a test mode for future chips).
AGCLF
AGC loop filter enable. Only applies to Path 1.The AGC loop is updated with the magnitude
of this sample (Path(1:0) = 01).
Path(1:0) Back End Data Routing Path Selection
00
Route output back to filter compute engine input to another FIR in the filter chain.
01
Route output thru the FIFO and AGC forward path to the cartesian-to-polar coordi-
nate converter conversion and output (I1, Q1, magnitude, phase, gain) and also to route to
a discriminator (i.e., d
φ
/dt FIR).
10
Route output directly to the output, bypassing the FIFO and AGC (I2, Q2). This path
also routes to next channel FIR input.
OS
Enable output strobe. Setting this bit generates a data ready signal when the data reaches
the output section and starts the serial output sequence (paths 1, 2, 3). If OS is not set,
there will be no output to the outside world from this channel, for that output calculation, but
the data will be loaded into its output holding register (OS would not be set when routing the
data to another back end when cascading channels).
FB
Feedback data path. When set, the magnitude and phase from the cartesian-to-polar coor-
dinate converter block are routed to the filter compute engine input. Provided for discrimina-
tor filtering.
F(4:0)
Filter select. For data recirculated to the input of the FIR processor by path 0 or from the
cartesian to polar coordinate converter output, these bits tell which filter sequencer step
gets it as an input.
26
25
24
23
FB
22
F4
21
F3
20
F2
19
F1
18
F0
31:29
Round Select
31:29
Round Select (Add rounding bit at specified location)
2
-24
, use this code when downshifting is not used.
2
-23
2
-22
2
-21
2
-20
2
-19
2
-18
no rounding
Provided for use with the coefficient down-shift bits.
000
001
010
011
100
101
110
111
41:32
Data Memory
Block Start
Memory block base address, 0-1023, 0-383 are valid for the HSP50216.
44:42
Data Memory
Block Size
44:42
0
1
2
3
4
5
6
7
(modulo addressing is used)
Block Size
8
16
32
64
128
256
512
1024
52:45
Data Memory
Block-to-Block Step
0-255, usually equal to the decimation factor for the FIR in this instruction.
INSTRUCTION BIT FIELDS (Continued)
BIT
POSITIONS
FUNCTION
DESCRIPTION
HSP50216
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