參數(shù)資料
型號： HSP50216KI
廠商： HARRIS SEMICONDUCTOR
元件分類： 無繩電話/電話
英文描述： Four-Channel Programmable Digital DownConverter
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196
封裝： BGA-196
文件頁數(shù)： 34/53頁
文件大小： 561K
代理商： HSP50216KI
34
7:0
First serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D.
Bit
Function
7
Sync generated. When set, a sync pulse is generated with the data slot (Serial Data Output 1 only, i.e., the sync is only
associated with Output 1). Set to zero for Output 2, SD2x.
6:3
Word width/format. All fixed point data is twos complement. The data is rounded (asymmetrically, with saturation) to the
desired number of bits.
0000
0-bit, fixed point (actually 1-bit position is used)
0001
4-bit, fixed point
0010
6-bit, fixed point
0011
8-bit, fixed point
0100
10-bit, fixed point
0101
12-bit, fixed point
0110
16-bit, fixed point
0111
20-bit, fixed point
1000
24-bit, fixed point
1001
32-bit fixed (8 LSBs are zeroed)
1010
32-bit, floating point, IEEE format
All other codes are invalid.
Note: Floating point format is only available on the Serial Data Output 1. Code 1010 is invalid on Serial Data Output 2.
2:0
Data type
000
Zeros
001
I1 (data routed from FIFO and AGC path)
010
Q1 (data routed from FIFO and AGC path)
011
Magnitude of I1/Q1
100
Phase (or d
φ
/dt) of I1/Q1
101
I2 (data routed directly from the filter processor)
110
Q2 (data routed directly from the filter processor)
111
AGC gain of I1/Q1 path
The filter processor must be programmed appropriately to route the data to I1/Q1 or I2/Q2.
NOTE:
Disable a slot by setting the 8-bit word to 00h. When disabled, a slot still uses one clock period. If, for example, the slots are
programmed to 16-bit, disabled, 16-bit, there would a one clock idle period between the two 16-bit data words.
If a new data sample occurs before the current set of data has been output, the new data will preempt the output and the first slot of
the new data will begin immediately. If a late sync was programmed, it will not occur.
0123456789ABCDEF0123456789ABCDEF
I,Q
012345678901234567890123ZZZZZZZZ
MAG
Z12345678901234567890123ZZZZZZZZ (MSB zero unless shifted)
PH
012345678901234567ZZZZZZZZZZZZZZ
AGC
Z12345678901234567ZZZZZZZZZZZZZZ (MSB zeroed)
TABLE 22. SERIAL DATA OUTPUT 1 CONTENT/FORMAT REGISTER 1 (IWA = *015h) (Continued)
P(15:0)
FUNCTION
TABLE 23. SERIAL DATA OUTPUT 1 CONTENT/FORMAT REGISTER 2 (IWA = *016h)
P(15:0)
FUNCTION
31:24
Set to zero
23:16
Seventh serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 of Table 22 for functional description of bits 23:16.
15:8
Sixth serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 of Table 22 for functional description of bits 15:8.
7:0
Fifth serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 of Table 22 for functional description of bits 7:0.
HSP50216
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