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參數(shù)資料
| 型號： | HSP50216KI |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Four-Channel Programmable Digital DownConverter |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196 |
| 封裝： | BGA-196 |
| 文件頁數(shù)： | 10/53頁 |
| 文件大?。?/td> | 561K |
| 代理商： | HSP50216KI |
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10
Filter Compute Engine
The filter compute engine is a dual multiply-accumulator
(MAC) data path with a microcoded FIR sequencer. The filter
compute engine can implement a single FIR or a set of
filters. For example, the filter chain could include two
halfband filters, a shaping (matched) filter and a resampling
filter. The following filter types are currently supported by the
architecture and microcode:
even symmetric w/ even # of taps decimation filters
even symmetric w/ odd # of taps decimation filters
(including HBFs)
odd symmetric w/ even # of taps decimation filters
odd symmetric w/ odd # of taps decimation filters
asymmetric decimation filters
complex filters
interpolation filters (up to interpolate by 4)
interpolation halfband filters
resampling filters (under NCO control)
fixed resampling ratio filter (within the available number
of coefficients)
quadrature to real filtering (w/ fs/4 up conversion)
The input to the filter compute engine comes from one of
three sources - a CIC filter output (which can also be another
backend section), the output of the filter compute engine (fed
back to the input) or the magnitude and d
φ
/dt fed back from
the cartesian-to-polar coordinate converter.
The number and size of the filters in the chain is limited by
the number of clock cycles available and by the data and
coefficient RAM/ROM resources. The data RAM is 384
words (I/Q pairs) deep. The data addressing is modulo in
power-of-2 blocks, so the maximum filter size is 256. The
block size and the block starting memory address for each
filter is programmable so that the available memory can be
used efficiently. The coefficient RAM is 192 words deep. It is
half the size of the data memory because filter coefficients
are typically symmetric. ROMs are provided with halfband
filter coefficients, resampling filter coefficients, and
constants. The filter compute engine exploits symmetry
where possible so that each MAC can compute two filter
taps per clock, by doing a pre-add before multiplying. In the
case of halfband filters, the zero-valued coefficients are
skipped for extra efficiency. There is an overhead of one
clock cycle per input sample for each filter in the chain (for
writing the data into the data RAM) and (except in special
cases) a two clock cycle overhead for the entire chain for
program flow control instructions.
The output of the filter compute engine is routed through a
FIFO in the main output path. The FIFO is provided to more
evenly space the FIR outputs when they are produced in
HSP50216
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| HSP50307EVAL1 | 2.0GHz to 2.7GHz DownConverter |
| HSP50415 | Wideband Programmable Modulator(寬帶可編程調(diào)制器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50216KIZ | 功能描述:上下轉(zhuǎn)換器 MULTI-CH PROGRAM CONV BGA PKG IND RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50306 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital QPSK Demodulator |
| HSP50306 WAF | 制造商:Intersil Corporation 功能描述: |
| HSP50306_04 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital QPSK Demodulator |
| HSP50306SC-25 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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