參數(shù)資料
型號： HSP50216KI
廠商： HARRIS SEMICONDUCTOR
元件分類： 無繩電話/電話
英文描述： Four-Channel Programmable Digital DownConverter
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196
封裝： BGA-196
文件頁數(shù)： 38/53頁
文件大?。?/td> 561K
代理商： HSP50216KI
38
7
CH0 Ext AGC input enable. 0=CH0 loop filt, 1=external input.
6
CH1 Ext AGC input enable 0=CH1 loop filt, 1=external input.
5
CH2 Ext AGC input enable 0=CH2 loop filt, 1=external input.
4
CH3 Ext AGC input enable Set to 0.
3
CH0 enable serial output 1=FIR0 out enabled to serial outputs.
2
CH1 enable serial output 1=FIR1 out enabled to serial outputs.
1
CH2 enable serial output 1=FIR2 out enabled to serial outputs.
0
CH3 enable serial output 1=FIR3 out enabled to serial outputs.
TABLE 34. BUS ROUTING CONTROL REGISTER (GWA = F801h) (Continued)
P(15:0)
FUNCTION
TABLE 35. RESET/SYNC/INTERRUPT SOURCE SELECTION REGISTER (GWA = F802h)
P(15:0)
FUNCTION
31
When set, an interrupt will be generated on each data output of channel 0 to the output block. Typically, this bit will only be set for
one channel.
30
When set, the input to the part will be disabled (the input enable will be zeroed and held at zero) on a
μ
P reset (this is always true
for the reset pin, whether this bit is set or not, and additionally, the reset pin sets the input mode to gated). The input enable will be
released for the input sample that aligns with the SYNCI signal. This is a method for starting up the processing synchronous with a
particular data sample.
29
When this bit is set, the carrier center frequency will be updated from the holding register to the active register on SYNCI signals. If
the bit is set in register IWA = *004h to clear the phase accumulator feedback on loading, this function will synchronize the phase of
multiple channels. After initial synchronization, the bit in IWA = *004h can be cleared and updates will be synchronous and phase
continuous across channels.
28
When this bit is set, the FIR filter compute engine is reset on SYNCI. Resetting the FIR filter compute engine requires 32 clock cycles
to initialize the read and write pointers.
27
When this bit is set, the AGC is reset on SYNCI.
26
This bit has the same function as bit 29, but for the timing (resampler) NCO. The bit to zero the phase accumulator feedback is in
register IWA = *00Ah.
25
When this bit is set, the CIC decimation counter is reset on SYNCI.
24
When this bit is set, the serial output block is reset on SYNCI. If bit 4 in location GWA F803h is set, the serial clock divider is also reset.
23:16
Same functions as 31:24 for channel 1.
15:8
Same functions as 31:24 for channel 2.
7:0
Same functions as 31:24 for channel 3.
TABLE 36. SERIAL CLOCK CONTROL REGISTER (GWA = F803h)
P(15:0)
FUNCTION
4
Enables resetting serial clock divider on SYNCI. When enabled, a SYNCI enabled for any of the serial data outputs in the Reset/Sync
register will reset the serial clock divider.
3
SCLK polarity.
1
0
Clock low to high transition occurs at the center of the data bit.
Clock high to low transition at the center of the data bit.
HSP50216
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