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參數(shù)資料
| 型號： | HSP50216KI |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Four-Channel Programmable Digital DownConverter |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196 |
| 封裝： | BGA-196 |
| 文件頁數(shù)： | 32/53頁 |
| 文件大?。?/td> | 561K |
| 代理商： | HSP50216KI |
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TABLE 20. AGC/DISCRIMINATOR CONTROL REGISTER (IWA = *013h)
P(15:0)
FUNCTION
10
μ
P AGC loop gain select.
9
Enable filter compute engine control of AGC loop gain. When this bit is set, a bit in the filter compute engine destination field selects
which loop gain to use with that filter output’s gain error. Setting bit 10 overrides this bit and forces a loop gain 1.
10:9
00
10
01
11
FUNCTION
Loop Gain 0 (
μ
P controlled)
Loop gain 1 (
μ
P controlled)
Loop Gain controlled by filter compute engine
Loop 1 (
μ
P override of filter compute engine)
8
Mean/Median. This bit controls the settling mode of the AGC. Mean mode settles to the mean of the signal and settles asymptotically
to the final value. Median mode settles to the median and settles with a fixed step size. This mode settles faster and more predictably,
but will have more AM after settling.
1
0
Mean mode
Median mode
7:6
Unused. Set to zero.
5
PhaseOutputSel
1
0
d
φ
/dt
Phase
4:3
DiscShift(1:0). Shifts the phase up 0, 1, 2, or 3-bit positions, discarding the bits shifted off the top. This makes the phase modulo 360,
180, 90, or 45 degrees to remove PSK modulation. The resulting phase is 18 bits.
2:0
DiscDelay(2:0). Sets the delay, in sample times, for the d
φ
/dt calculation.
000
111
1
8
TABLE 21. SERIAL DATA OUTPUT CONTROL REGISTER (IWA = *014h)
P(15:0)
FUNCTION
28
Sync polarity
1
0
Active low (low for one serial clock per word with a sync).
Active high.
27:26
Reserved, set to zero.
25:24
Sync position. This applies to all time slots in the serial output. The Sync programming is associated with the SD1x serial output data
stream (x = A, B, C, or D).
00
01
1X
Sync is asserted during the clock period following the last data bit of the word (early sync).
Sync is asserted during the serial clock period prior to the first data bit of the serial word (late sync).
Sync is asserted during the serial clock period of the first data bit of the serial word (coincident sync).
23:22
Reserved, set to zero.
HSP50216
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50216KIZ | 功能描述:上下轉(zhuǎn)換器 MULTI-CH PROGRAM CONV BGA PKG IND RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50306 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital QPSK Demodulator |
| HSP50306 WAF | 制造商:Intersil Corporation 功能描述: |
| HSP50306_04 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital QPSK Demodulator |
| HSP50306SC-25 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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