
28
3
Interpolated/Gated Mode Select
0
1
Gated. The carrier NCO and CIC are updated once per clock when ENIx is asserted.
Interpolated. The CIC is updated every clock. The carrier NCO is updated once per clock when ENIx is asserted. The
input is zeroed when ENIx is high.
2
Enable COF/COFSYNC inputs. When set, this bit enables two bits from the D(15:0) input data bus to be used as a carrier offset
frequency input.
1
Enable SOF/SOFSYNC inputs. When set, this bit enables two bits from the D(15:0) input data bus to be used as a resampler offset
frequency input.
0
Enable PN. When set, A PN code, weighted by the gain in location *001, is added to the input samples at the output of the mixer.
TABLE 1. CHANNEL INPUT SELECT/FORMAT REGISTER (IWA = *000h)
P(15:0)
FUNCTION
TABLE 2. PN GAIN REGISTER (IWA = *001h)
P(15:0)
FUNCTION
31:16
Reserved, set to all 0’s.
15:0
PN generator gain register. This input is provided to reduce the sensitivity of the receiver. A PN code, weighted by the value in this
location, is added to the data at the output of the mixer. Adding noise has the effect of increasing the receiver noise figure. One
reason to do this would be to decrease the basestation cell size in small steps. This method is very accurate and repeatable and can
be done on a FDM channel by channel basis. It does, however, reduce the overall dynamic range. An alternate way is to add
attenuation at the RF and adjust the whole range upward. This does not reduce the overall range but only shift it, with the shift being
done on all channels simultaneously.
TABLE 3. CIC DECIMATION FACTOR REGISTER (IWA = *002h)
P(15:0)
FUNCTION
15:0
Load with the desired CIC decimation factor minus 1.
TABLE 4. CIC DESTINATION FIR AND OUTPUT ENABLE/DISABLE REGISTER (IWA = *003h)
P(15:0)
FUNCTION
5:1
CIC output destination (FIR # in FIR processor). Usually set to 00001.
0
CIC output enable. Active high. When low, the data writes from the CIC to the filter compute engine are inhibited.
TABLE 5. CARRIER NCO/CIC CONTROL REGISTER (IWA = *004h)
P(15:0)
FUNCTION
31:19
Reserved, set to zero.
18:14
CIC barrel shift control.
00000 is the minimum shift factor and 11111 is maximum shift factor. This compensates for the CIC filter gain of R
N
, where N is the
number of enabled CIC stages and R is the CIC decimation factor. The equation used to compute the shift factor is:
Shift Factor = 45 - Ceiling(log
2
(R
N
)).
Examples:
N
5
5
R
512
8
Shift Factor
0
30
13:9
CIC stage bypasses. The integrator/comb pairs are numbered 1 thru 5 with 1 being the first integrator and first comb. Bit 13 bypasses
the first integrator/comb pair, bit 12 bypasses the second, etc. The first integrator is the largest. Typically, the stages are enabled
starting with stage 1 for maximum decimation range.
8:6
Carrier phase shift. Phase shifts of N*(
π
/4), N = 0 to 7.
5
Clear feedback (test signal or for mixer bypass).
4
NCO clear feedback on load.
3
Update frequency on SYNCI. Redundant. Set to1. See GWA register F802h.
HSP50216