參數(shù)資料
型號(hào)： HSP50216KI
廠商： HARRIS SEMICONDUCTOR
元件分類： 無繩電話/電話
英文描述： Four-Channel Programmable Digital DownConverter
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196
封裝： BGA-196
文件頁數(shù)： 11/53頁
文件大小： 561K
代理商： HSP50216KI
11
bursts (as when computing interpolation filters). The FIFO is
four samples deep. The FIFO is loaded by the output of the
filter when that path is selected. It is unloaded by a counter.
The spacing of the output samples is specified in clock
periods. The spacing can be from 1 (fall through) to 4096
samples (approximately the spacing for a 16KSPS output
sample rate when using 65MSPS clock).
The number and order of the filtering in the filter chain is
defined by a FIR control program. The FIR control program
is a sequence of up to 32 instruction words. Each instruction
word can be a filter or program flow instruction. The filter
instruction defines a FIR in the chain, specifying the type of
FIR, number of taps, decimation, memory allocation, etc. For
program flow, a wait for input sample(s) instruction, a loop
counter load, and several jumps (conditional and
unconditional) are provided.
The simplest filter program computes a single filter. It has
three instructions (see Sample Filter #1Program Instructions
below):
The parameters of the FIR (including type, number of taps,
decimation and memory usage) are specified in the bit fields
of the step 2 instruction word. To change the filtering the only
other change needed is the number of samples in the wait
threshold register. The filter in this example requires 52 clock
cycles to compute, allocated as follows:
Using a 65MSPS clock, the output sample rate could be as
high as 1.25MSPS. The input sample rate from the CIC filter
would be 2.5MSPS. The impulse response length would be
38
μ
sec (95 taps at 0.4
μ
s/tap).
Each additional filter added to the signal processing chain
requires one instruction step. As an example of this, a typical
filter chain might consist of two decimate-by-2 halfband
filters being followed by a shaping filter with the final filter
being a resampling filter. The program for this case might be
(see Sample Filter Program #2 Instructions below):
SAMPLE FILTER #1 PROGRAM
STEP
INSTRUCTION
0
Wait for enough input samples
(equal to the decimation factor)
1
FIR
Type = even symmetric
95 taps
Dec x 2
Compute one output
Decrement wait counter
Memory block size 128
Memory block start at 64,
Coefficient block start at 64
Step size 1
Output to AGC
2
Jump, Unconditional, to step 0
SAMPLE FILTER #1 CLOCK CYCLES CALCULATION
CLOCK
CYCLES
FUNCTION PERFORMED
48
Clocks for FIR computation (two taps/clock due to
symmetry)
2
Clocks for writing the input data into the data RAMs
(Decimate by 2 requires 2 inputs per output)
2
Clocks for the program flow instructions (wait and
jump)
52
Total
SAMPLE FILTER #2 PROGRAM
STEP
INSTRUCTION
0
Wait for enough input samples (usually equal to the
total decimation - 8 in this case)
1
FIR
Type = even symmetry
15 taps
Halfband
Dec x 2
Compute four outputs
Memory block size 32
Memory block start at 0
Coefficient block start at 13
Output to step 2
Decrement wait count
2
FIR
Type = even symmetry
23 taps
Halfband
Dec x 2
Compute two outputs
Memory block size 32
Memory block start at 32
Coefficient block start at 24
Output to step 3
3
FIR
Type = even symmetry
95 taps
Dec x 2
Compute one output
Memory block size 128
Memory block start at 64
Coefficient block start at 64
Step size 1
Output to step 4
4
FIR
Type = resampler
Increment NCO
6 taps
Compute one output
Memory block size 8
Memory block starts at 192
Coefficient block start at 512
Step size 32
Output to AGC
5
Jump, Unconditional, to 0
HSP50216
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