參數(shù)資料
型號： HSP50216KI
廠商： HARRIS SEMICONDUCTOR
元件分類： 無繩電話/電話
英文描述： Four-Channel Programmable Digital DownConverter
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196
封裝： BGA-196
文件頁數(shù)： 12/53頁
文件大?。?/td> 561K
代理商： HSP50216KI
12
Sample filter #2 requires:
32 + 32 + 128 + 8 = 200 data RAM locations
(95+1)/2=48 coefficient RAM location (resampler and
HBF coefficient are in ROM).
The number of clock cycles required to compute an output
for Sample filter #2 is calculated as follows:
Total decimation is 8, so the input sample rate for the FIR
chain could be up to:
f
CLK
/(ceil(105/8)) = f
CLK
/14.
With a 65MHz clock, this would support a maximum input
sample rate to the FIR processor of 4.6MHz and an output
sample rate up to 0.580MHz. The shaping filter impulse
response length would be:
(95 x 2)/580,000 = 82
μ
s.
The maximum output sample rate is dependent on the
length and number of FIRs and their decimation factors.
Illustrating this concept with Filter Example #3, a higher
speed filter chain might be comprised of one decimate-by-2
halfband filter (15 taps) followed by a 30 tap shaping FIR
filter with no decimation. The program for this example could
be:
The number of clock cycles required to compute an output
for Sample filter #3 is calculated as follows:
For Filter Example #3 and a 65MSPS input, the maximum
output sample rate would be 2.5MSPS and the maximum
FIR processor input sample rate would be 5MSPS (At
80MSPS, the FIR could be up to 42 taps).
Channels 0, 1, 2 and 3 can be combined in a polyphase
structure for increased bandwidth or improved filtering.
Filter Example #4 will be used to demonstrate this capability.
Symbol rate of 4.096 MSym. The desired output sample rate
is 8.192MSPS. Arrange the four back end sections as four
filters operating on the same CIC output at a rate of
65.536MHz/4=16.384MHz.
Each channel computes the same sequence, offset by one
output sample from the previous sample. Each channel
decimates down to 2.048M and then the channels are
SAMPLE FILTER #2 CLOCK CYCLES CALCULATION
CLOCK
CYCLES
FUNCTION PERFORMED
20
Halfband 1 compute clocks
(5 per compute x4 computes)
8
Halfband 1 input sample writes
14
Halfband 2 compute clocks
(7 per compute x2 computes)
4
Halfband 2 input sample writes
48
48 x 1 FIR compute clocks
2
FIR input sample writes
6
6 x 1 resampler compute clocks
1
Resampler input sample writes
1
Jump instruction
1
Wait instruction
105
Clock cycles per output
SAMPLE FILTER #3 PROGRAM
STEP
INSTRUCTION
0
Wait for enough input samples (2 in this case)
1
FIR
Type = even symmetry
19 taps
Halfband
Dec x 2
Compute one output
Memory block size 32
Memory block start at 0
Coefficient block start at 18
Output to step 2
Reset wait count
2
FIR
Type = even symmetry
30 taps
Dec x 1
Compute one output
Memory block size 64
Memory block start at 32
Coefficient block start at 64
Step size 1
Output to AGC
3
Jump, Unconditional, to 0
SAMPLE FILTER #3 CLOCK CYCLES CALCULATION
CLOCK
CYCLES
FUNCTION PERFORMED
6
6 x 1 HBF compute clocks
2
HBF input writes
15
15 x 1 FIR compute clocks
1
1 FIR input write
1
1 wait
1
1 jump
26
Clock cycles per output
HSP50216
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