
41
Table of Indirect Read Address (IRA) Registers
The address decoding for the read source locations is given below. The internal address of the data to be read is written to direct
address 3 (ADD(2:0) = 3) to select and/or fetch the data. A strobe is generated, if needed, to fetch or stabilize the data for reading.
If a strobe is needed, the indirect read address must be written to direct address 3 each time the data is needed. If a strobe is not
needed, the data can be read repeatedly at direct addresses 0 and 1(ADD(2:0) = 0 and 1, respectively) with any changes in the
data showing up immediately. The strobe to sample the AGC gain is generated separately by an indirect write (see IWA *00Fh in
the Tables of Indirect Write Address Registers). This allows the AGC gain of all the channels to be sampled simultaneously.
NOTE: These Indirect Read Addresses are repeated for each channel. In the addresses below, the
*
field is the channel select nibble. These bits
of the Indirect Address select the target channel register for the data being read. Values of 0 through 3 and F are valid.
TABLE 43.
μ
P FIFO READ ORDER CONTROL REGISTER (GWA = F820h thru F83Fh)
P(15:0)
FUNCTION
4:0
The five bits selecting the data type are encoded as follows:
C C D D D,
where CC is the channel number and DDD is the data type.
DDD
Data Type
000
I(23:8)
001
I(7:0),8*zeros
010
Q(23:8)
011
Q(7:0),8*zero
100
Mag(23:8)
101
Mag(7:0),8*zero
110
Phase(15:0)
111
AGC gain (15:0)
The upper 16 bits of the I data path via the FIFO/AGC.
The lower 8 bits of the I data path.
The upper 16 bits of the Q data path via the FIFO/AGC.
The lower 8 bits of the Q data path.
The upper 16 bits of magnitude (after the gain adjust described in channel register)
The lower 8 bits of magnitude.
The upper 16 bits of phase.
The upper 16 bits of the AGC gain.
TABLE 44. TABLE OF INDIRECT READ ADDRESS (IRA) REGISTERS
IRA
FUNCTION
*006h
Active Carrier NCO Center Frequency
*00Ch
Wait Preload, Decr 1&2
*009h
Active Timing NCO Center Freq (Most Significant 32 bits)
*00Fh
AGC gain
*100h - *17Fh
Instruction RAMs
*180h - *1FCh
Instruction RAMs (pointer DRAM)
*400h - *43Fh
Coefficient ROM -HBF, const.
*440h - *47Fh
Coefficient RAM -1
*480h - *4FFh
Coefficient RAM -2
*500h - *5FFh
Coefficient ROM -Resampler
F806h
Input Level Detector Output
HSP50216