參數(shù)資料
型號(hào)： HSP50216KI
廠商： HARRIS SEMICONDUCTOR
元件分類： 無(wú)繩電話/電話
英文描述： Four-Channel Programmable Digital DownConverter
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196
封裝： BGA-196
文件頁(yè)數(shù)： 40/53頁(yè)
文件大?。?/td> 561K
代理商： HSP50216KI
40
3
Interpolated/Gated Mode Select
0
Gated. The carrier NCO and CIC are updated once per clock when ENIx is asserted.
1
Interpolated. The CIC is updated every clock. The carrier NCO is updated once per clock when ENIx is asserted. The input is
zeroed when ENIx is high.
2:0
Unused. Set to 0.
TABLE 37. INPUT LEVEL DETECTOR SOURCE SELECT/FORMAT REGISTER (GWA = F804h) (Continued)
P(15:0)
FUNCTION
TABLE 38. INPUT LEVEL DETECTOR CONFIGURATION REGISTER (GWA = F805h)
P(15:0)
FUNCTION
21
1
0
Ones complement of 16-bit data after formatting.
Unmodified input.
20
1
0
This bit may also be set low temporarily when free running to stabilize the accumulator data for reading.
Free run (ignore interval counter).
Stop when interval counter times out.
19:18
Input Level Detector Leak factor, A.
00
1
2
-8
2
-12
2
-16
01
10
11
17:16
Input Level Detector Mode
00
Leaky integrator (Y
n
= A*X
n
+ (1-A)*Y
n-1
, where A is the gain selected in bits 19:18).
01
Peak detector.
10
Integrator (bit 20 should be set to 0).
15:0
Input Level Detector Interval
Load with two less than the desired number of input samples. The interval range is 2 to 65537 input samples.
TABLE 39. INPUT LEVEL DETECTOR START STROBE REGISTER (GWA = F806h)
P(15:0)
FUNCTION
N/A
Writing to this location clears the input level detector accumulator and restarts the interval counter. When the interval counter is done,
bit 1 of the status word is set.
TABLE 40.
μ
P/TEST INPUT BUS REGISTER (GWA = F807h)
P(15:0)
FUNCTION
15:0
This 16-bit value can be used as the input to one or more NCO/Mixer/CIC sections for test or to set the input to a constant value to
minimize power when the channel is not in use.
The ENI signal for this input is either bit 11 in the channel register at IWA *000h or the strobe generated by a write to location GWA
F808h (selected via bit 12 of the channel register at IWA *000h).
TABLE 41.
μ
P/TEST INPUT BUS ENI REGISTER (GWA = F808h)
P(15:0)
FUNCTION
N/A
A write to this location, generates and ENI strobe for the
μ
P driven input port (when selected via bit 12 of IWA *000h).
TABLE 42. SYNCO STROBE REGISTER (GWA = F809h)
P(15:0)
FUNCTION
N/A
A write to this location will cause a one-clock-wide pulse on the SYNCO pin. The SYNCO pin is used to synchronize multiple channels
or parts. The SYNCO pin from one part is typically connected to the SYNCI pin of all the parts. Up to two pipeline registers may be
inserted in the SYNCO to SYNCI path.
HSP50216
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