參數(shù)資料
型號： HSP50216KI
廠商： HARRIS SEMICONDUCTOR
元件分類： 無繩電話/電話
英文描述： Four-Channel Programmable Digital DownConverter
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196
封裝： BGA-196
文件頁數(shù)： 24/53頁
文件大?。?/td> 561K
代理商： HSP50216KI
24
first data time slot = I, 32-bit (IWA = 0015h, bits 7:0);
second data time slot = Q, 32-bit (IWA = 0015h, bits 15:8);
third through seventh data time slot = zero and no sync,(IWA
= 0015h, bits 31:16 and IWA = 0016h, bits 31:0);
enable the serial output for this channel in the serial routing
mask (IWA = 0014h, bit 16).
Channel 1:
delay = 64(IWA = 1014h, bits 11:0);
first data time slot = I, 32-bit (IWA = 1015h, bits 7:0);
second data time slot = Q, 32-bit (IWA = 1015h, bits 15:8);
third through seventh data time slot = zero and no sync,
(IWA = 1015h, bits 31:16 and IWA = 1016h, bits 31:0);
enable the serial output for this channel in the serial routing
mask (IWA = 1014h, bit 16).
The syncs for the I and Q data are programmed as desired.
The resulting order is CH0I first, then CH0Q, CH2I, and
CH2Q.
As an example when no multiplexing of channel data is
desired:
IWA = 0014h, bit 12 for channel 0 would be set;
IWA = 1014h, bit 13 in channel 1 would be set;
IWA = 2014h, bit 14 in channel 2 would be set, and
IWA = 3014h, bit 15 in channel 3 would be set
allowing four serial data streams to be output on SD2A,
SD2B, SD2C, and SD2D. The other bits in each channel’s
mask would be cleared (programmed to 0).
Microprocessor Interface
The HSP50216 Microprocessor (
μ
P) interface consists of a
16-bit bidirectional data bus, P(15:0), three address pins,
ADD(2:0), a write strobe (WR), a read strobe (RD) and a
chip enable (CE). Indirect addressing is used for control and
configuration of the HSP50216. The control and
configuration data to be loaded is first written to a 32-bit
holding register at direct (external) addresses ADD(2:0) = 0
and 1, 16 bits at a time. The data is then transferred to the
target register, synchronous to the clock, by writing the
indirect (internal) address of the target register to direct
(external) address 2, ADD(2:0) = 2. The interface generates
a synchronous one clock cycle wide strobe to transfer the
data contained in the holding register to the target register.
The synchronization and write process requires 4 clock
periods. New data
should not
be written to the holding
register until after the synchronization period is over.
Data reads can be direct, indirect or FIFO-like depending on
the data that is being read. The status register is read
directly at direct (external) address 3, ADD(2:0) = 3.
Readback of internal registers and memories is indirect. The
16-bit indirect (internal) address of the desired read source
is first written to direct (external) address 3, ADD(2:0) = 3, to
select the data. The data can then be read at direct
HSP50216
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