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| 型號： | EVAL-ADUC7023QSPZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 81/96頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADUC7023 |
| 標準包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC7023 |
| 所含物品： | 板 |
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ADuC7023
Data Sheet
| Page 82 of 96
FIQSTAN Register
If IRQCONN Bit 1 is asserted and FIQVEC is read, then one of
these bits assert. The bit that asserts depends on the priority of
the FIQ. If the FIQ is of Priority 0, then Bit 0 asserts. If the FIQ
is of Priority 1, then Bit 1 asserts, and so forth.
When a bit is set in this register, all interrupts of that priority
and lower are blocked.
To clear a bit in this register, all bits of a higher priority must be
cleared first. It is only possible to clear one bit at a time. For
example, if this register is set to 0x09, then writing 0xFF changes
the register to 0x08 and writing 0xFF a second time changes the
register to 0x00.
Name:
FIQSTAN
Address:
0xFFFF013C
Default value: 0x00000000
Access:
Read/write
Table 98. FIQSTAN MMR Bit Designations
Bit
Name
Description
31 to 8
Reserved
These bits are reserved and should not be
written to.
7 to 0
This bit is set to 1 to enables nesting of
FIQ interrupts.
When this bit is cleared, it means no
nesting or prioritization of FIQs is
allowed.
External Interrupts and PLA interrupts
The ADuC7023 provides up to four external interrupt sources
and two PLA interrupt sources. These external interrupts can be
individually configured as level or rising/falling edge triggered.
To enable the external interrupt source or the PLA interrupt
source, the appropriate bit must be set in the FIQEN or IRQEN
register. To select the required edge or level to trigger on, the
IRQCONE register must be appropriately configured.
To properly clear an edge-based external IRQ interrupt or an edge-
based PLA interrupt, set the appropriate bit in the IRQCLRE
register.
IRQCONE Register
Name:
IRQCONE
Address:
0xFFFF0034
Default value: 0x00000000
Access:
Read and write
Table 99. IRQCONE MMR Bit Designations
Bit
Value
Name
Description
31 to 12
Reserved
These bits are reserved and
should not be written to.
11 to 10
11
PLA1SRC[1:0]
PLA IRQ1 triggers on falling
edge.
10
PLA IRQ1 triggers on rising
edge.
01
PLA IRQ1 triggers on low
level.
00
PLA IRQ1 triggers on high
level.
9 to 8
11
IRQ3SRC[1:0]
External IRQ3 triggers on
falling edge.
10
External IRQ3 triggers on
rising edge.
01
External IRQ3 triggers on
low level.
00
External IRQ3 triggers on
high level.
7 to 6
11
IRQ2SRC[1:0]
External IRQ2 triggers on
falling edge.
10
External IRQ2 triggers on
rising edge.
01
External IRQ2 triggers on
low level.
00
External IRQ2 triggers on
high level.
5 to 4
11
PLA0SRC[1:0]
PLA IRQ0 triggers on falling
edge.
10
PLA IRQ0 triggers on rising
edge.
01
PLA IRQ0 triggers on low
level.
00
PLA IRQ0 triggers on high
level.
3 to 2
11
IRQ1SRC[1:0]
External IRQ1 triggers on
falling edge.
10
External IRQ1 triggers on
rising edge.
01
External IRQ1 triggers on
low level.
00
External IRQ1 triggers on
high level.
1 to 0
11
IRQ0SRC[1:0]
External IRQ0 triggers on
falling edge.
10
External IRQ0 triggers on
rising edge.
01
External IRQ0 triggers on
low level.
00
External IRQ0 triggers on
high level.
Rev. E
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