參數(shù)資料
型號(hào)： EVAL-ADUC7023QSPZ1
廠商： Analog Devices Inc
文件頁數(shù)： 37/96頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7023
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC7023
所含物品： 板
ADuC7023
Data Sheet
| Page 42 of 96
REMAP Register
Name:
REMAP
Address:
0xFFFF0220
Default value:
0x00
Access:
Read/write
Table 36. REMAP MMR Bit Designations
Bit
Name
Description
7 to 5
Reserved.
4
Read-only bit. Indicates the size of the
Flash/EE memory available. If this bit is set,
only 32 kB of Flash/EE memory is available.
3
Read-only bit. Indicates the size of the
SRAM memory available. If this bit is set,
only 4 kB of SRAM is available.
2 to 1
JTAFO
Read only bits. See the P0.0/BM
description for further details.
If = [00], then P0.1/P0.2/P0.3 are
configured as JTAG pins.
If = [1x], then P0.1/P0.2/P0.3 are
configured as GPIO pins.
These bits are configured by the kernel
after any reset sequence and depend on
the state of P0.0 during the last reset
sequence.
0
Remap
Remap bit.
This bit is set by the user to remap the
SRAM to Address 0x00000000.
This bit is cleared automatically after reset
to remap the Flash/EE memory to Address
0x00000000.
Reset Operation
There are four kinds of reset: external, power-on, watchdog
expiration, and software force. The RSTSTA register indicates
the source of the last reset, and RSTCLR allows clearing of the
RSTSTA register. These registers can be used during a reset
exception service routine to identify the source of the reset. If
RSTSTA is null, the reset is external.
The RSTCFG register allows different peripherals to retain their
state after a watchdog or software reset.
RSTSTA Register
Name:
RSTSTA
Address:
0xFFFF0230
Default value: 0x01
Access:
Read/write
Table 37. RSTSTA MMR Bit Designations
Bit
Description
7 to 3
Reserved.
2
Software reset.
This bit is set by the user to force a software reset.
This bit is cleared by setting the corresponding bit
in RSTCLR.
1
Watchdog timeout.
This bit is set automatically when a watchdog
timeout occurs.
This bit is cleared by setting the corresponding bit
in RSTCLR.
0
Power-on reset.
This bit is set automatically when a power-on reset
occurs.
This bit is cleared by setting the corresponding bit
in RSTCLR.
RSTCLR Register
Name:
RSTCLR
Address:
0xFFFF0234
Default value: 0x00
Access:
Write
Function:
Note that to clear the RSTSTA register, users
must write the Value 0x07 to the RSTCLR
register.
RSTCFG Register
Name:
RSTCFG
Address:
0xFFFF024C
Default value: 0x00
Access:
Read/write
Table 38. RSTCFG MMR Bit Designations
Bit
Description
7 to 3
Reserved. Always set to 0.
2
This bit is set to 1 to configure the DAC outputs to retain
their state after a watchdog or software reset.
This bit is cleared for the DAC pins and registers to
return to their default state.
1
Reserved. Always set to 0.
0
This bit is set to 1 to configure the GPIO pins to retain
their state after a watchdog or software reset.
This bit is cleared for the GPIO pins and registers to
return to their default state.
Rev. E
相關(guān)PDF資料
PDF描述
AIUR-10-182K INDUCTOR POWER 1800UH 10% T/H
EYM15DRSD CONN EDGECARD 30POS DIP .156 SLD
V300C3V3C50B CONVERTER MOD DC/DC 3.3V 50W
AIUR-06-271K INDUCTOR POWER 270UH 10% T/H
EGM15DRSD CONN EDGECARD 30POS DIP .156 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-ADuC7023QSPZ2 制造商:AD 制造商全稱:Analog Devices 功能描述:Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU with Enhanced IRQ Handler
EVALADUC7023QSPZU1 制造商:Analog Devices 功能描述:
EVAL-ADUC7024QS 制造商:Analog Devices 功能描述:QUICK START DEVELOPMENT SYSTEM - Bulk
EVAL-ADUC7024QS-U2 制造商:Analog Devices 功能描述:QUICK START DEVL SYST EVAL BOARD I.C. - Bulk
EVAL-ADUC7024QS-U3 制造商:Analog Devices 功能描述:ARM7 ADUC7024 QUICKSTART DEV KIT
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*