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| 型號： | EVAL-ADUC7023QSPZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 67/96頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADUC7023 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC7023 |
| 所含物品： | 板 |
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Data Sheet
ADuC7023
| Page 7 of 96
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
INTERNAL OSCILLATOR
32.768
kHz
±3
%
MCU CLOCK RATE
From 32 kHz Internal Oscillator
326
kHz
CD = 7
From 32 kHz External Crystal
41.78
MHz
CD = 0
Using an External Clock
0.05
44
MHz
TA = 85°C
0.05
41.78
MHz
TA = 125°C
START-UP TIME
Core clock = 41.78 MHz
At Power-On
66
ms
From Pause/Nap Mode
24
ns
CD = 0
3.07
s
CD = 7
From Sleep Mode
1.58
ms
From Stop Mode
1.7
ms
PROGRAMMABLE LOGIC ARRAY (PLA)
Pin Propagation Delay
12
ns
From input pin to output pin
Element Propagation Delay
2.5
ns
POWER REQUIREMENTS14, 15
Power Supply Voltage Range
AVDD to AGND and IOVDD to DGND
2.7
3.6
V
Analog Power Supply Currents
AVDD Current
200
A
ADC in idle mode
Digital Power Supply Current
IOVDD Current in Normal Mode
Code executing from Flash/EE
8.5
10
mA
CD = 7
11
15
mA
CD = 3
28
35
mA
CD = 0 (41.78 MHz clock)
IOVDD Current in Pause Mode
14
20
mA
CD = 0 (41.78 MHz clock)
IOVDD Current in Sleep Mode
230
650
A
TA = 125°C
Additional Power Supply Currents
ADC
1.4
mA
At 1 MSPS
0.7
mA
At 62.5 kSPS
DAC
400
A
Per DAC
ESD TESTS
2.5 V reference, TA = 25°C
HBM Passed
3
kV
FICDM Passed
1.0
kV
1
All ADC channel specifications are guaranteed during normal microcontroller core operation.
2
Apply to all ADC input channels.
3
Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN).
4
Not production tested but supported by design and/or characterization data on production release.
5
Measured using the factory-set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 28. Based on external ADC
system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section).
6
The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified.
7
DAC linearity is calculated using a reduced code range of 100 to 3995.
8
DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF.
9
DAC linearity is calculated using a reduced code range of 100 to 3995.
10
DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF.
11
Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at 40°C, +25°C, +85°C, and +125°C.
12
Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature.
13
Test carried out with a maximum of eight I/Os set to a low output level.
14
Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with
3.6 V supply, and sleep mode with 3.6 V supply.
15
IOVDD power supply current decreases typically by 2 mA during a Flash/EE erase cycle.
Rev. E
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| EVAL-ADuC7023QSPZ2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU with Enhanced IRQ Handler |
| EVALADUC7023QSPZU1 | 制造商:Analog Devices 功能描述: |
| EVAL-ADUC7024QS | 制造商:Analog Devices 功能描述:QUICK START DEVELOPMENT SYSTEM - Bulk |
| EVAL-ADUC7024QS-U2 | 制造商:Analog Devices 功能描述:QUICK START DEVL SYST EVAL BOARD I.C. - Bulk |
| EVAL-ADUC7024QS-U3 | 制造商:Analog Devices 功能描述:ARM7 ADUC7024 QUICKSTART DEV KIT |
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