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| 型號： | EVAL-ADUC7023QSPZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 44/96頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADUC7023 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC7023 |
| 所含物品： | 板 |
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Data Sheet
ADuC7023
| Page 49 of 96
MMRs and Keys
The operating mode, clocking mode, and programmable clock
divider are controlled via three MMRs, PLLCON (see Table 49)
and POWCONx. PLLCON controls the operating mode of the
clock system, POWCON0 controls the core clock frequency and
the power-down mode, POWCON1 controls the clock
frequency to I2C and SPI.
To prevent accidental programming, a certain sequence has to
be followed to write to the PLLCON and POWCONx registers.
PLLKEY1 Register
Name:
PLLKEY1
Address:
0xFFFF0410
Default value: 0xXXXX
Access:
Write
PLLKEY2 Register
Name:
PLLKEY2
Address:
0xFFFF0418
Default value: 0xXXXX
Access:
Write
PLLCON Register
Name:
PLLCON
Address:
0xFFFF0414
Default value: 0x21
Access:
Read/write
Table 49. PLLCON MMR Bit Designations
Bit
Value
Name
Description
7 to 6
Reserved.
5
OSEL
32 kHz PLL input selection. This bit
is set by the user to select the internal
32 kHz oscillator. This bit is set by
default. This bit is cleared by the user
to select the external 32 kHz crystal.
4 to 2
Reserved.
1 to 0
MDCLK
Clocking modes.
00
Reserved.
01
PLL default configuration.
10
Reserved.
11
External clock on Pin 33 (40-lead
LFCSP)/Pin 25 (32-lead LFCSP).
Table 50. PLLCON Write Sequence
Name
Code
PLLKEY1
0xAA
PLLCON
User value
PLLKEY2
0x55
POWKEY1 Register
Name:
POWKEY1
Address:
0xFFFF0404
Default value:
0xXXXX
Access:
Write
Function:
POWKEY1 prevents accidental
programming to POWCON0.
POWKEY2 Register
Name
POWKEY2
Address
0xFFFF040C
Default value
0xXXXX
Access
Write
Function:
POWKEY2 prevents accidental
programming to POWCON0.
POWCON0 Register
Name:
POWCON0
Address:
0xFFFF0408
Default value:
0x00
Access:
Read/write
Table 51. POWCON0 MMR Bit Designations
Bit
Value
Name
Description
7
Reserved.
6 to 4
PC
Operating modes.
000
Active mode.
001
Pause mode.
010
Nap.
011
Sleep mode. IRQ0 to IRQ3 can wake
up the part.
100
Stop mode. IRQ0 to IRQ3 can wake
up the part.
Others
Reserved.
3
Reserved.
2 to 0
CD
CPU clock divider bits.
000
41.78 MHz.
001
20.89 MHz.
010
10.44 MHz.
011
5.22 MHz.
100
2.61 MHz.
101
1.31 MHz.
110
653 kHz.
111
326 kHz.
Rev. E
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