參數(shù)資料
型號： EVAL-ADUC7023QSPZ1
廠商： Analog Devices Inc
文件頁數(shù)： 6/96頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7023
標準包裝： 1
系列： QuickStart™ PLUS 套件
類型： MCU
適用于相關產(chǎn)品： ADuC7023
所含物品： 板
ADuC7023
Data Sheet
| Page 14 of 96
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NOTES
1. EXPOSED PAD. THE PADDLE NEEDS TO BE SOLDERED AND
EITHER CONNECTED TO AGND OR LEFT FLOATING.
08675-
048
1
AVDD
2
GNDREF
3
DAC0
4
DAC1
5
DAC2
6
DAC3
7
P1.4/ADC10/PLAO[3]
8
P2.0/ADC12/PWM4/PLAI[7]
9
10
P0.5/SDA0/PLAI[1]/COMPOUT
23 RTCK
24 TMS
25 P0.0/nTRST/ADCBUSYPLAI[8]/BM
26 P0.1/PLAI[9]/TDO
27 P0.2/PLAO[8]/TDI
28 P0.3/PLAO[9]/TCK
29 P1.5/ADC6/PWMTRIPINPUT/PLAO[4]
30 P2.2/ADC7/SYNC/PLAO[6]
22 XCLKO
21 XCLKI
1
P
0
.6
/M
IS
O
/S
C
L
1
/P
L
A
I[
2
]
1
2
P
0
.7
/M
O
S
I/
S
D
A
1
/P
L
A
O
[0
]
1
3
P
1
.0
/S
P
IC
L
K
/P
W
M
0
/P
L
A
O
[1
]
1
5
P
1
.6
/P
W
M
2
/S
C
L
1
/P
L
A
I[
5
]
1
7
D
G
N
D
1
6
P
1
.7
/P
W
M
3
/S
D
A
1
/P
L
A
I[
6
]
1
8
IO
V
D
1
9
L
V
D
2
0
3
P
1
.2
/A
D
C
4
/I
R
Q
2
/P
L
A
I[
3
]/
E
C
L
K
3
4
P
1
.3
/A
D
C
5
/I
R
Q
3
/P
L
A
I[
4
]
3
5
V
R
E
F
3
6
A
D
C
0
3
7
A
D
C
1
3
8
A
D
C
2
/C
M
P
0
3
9
A
D
C
3
/C
M
P
1
4
0
A
G
N
D
3
2
P
2
.4
/A
D
C
9
/P
L
A
I[
1
0
]
3
1
P
2
.3
/A
D
C
8
/P
L
A
O
[7
]
ADuC7023
TOP VIEW
(Not to Scale)
R
S
T
1
4
P
1
.1
/S
S
/I
R
Q
1
/P
W
M
1
/P
L
A
O
[2
]/
T
I
P0.4/IRQ0/SCL0/PLAI[0]/CONVSTART
Figure 7. 40-Lead LFCSP Pin Configuration
0
867
5-
00
7
AVDD
GNDREF
DAC0
DAC1
DAC2
DAC3
P0.5/SDA0/PLAI[1]/COMPOUT
P0.3/PLAO[9]/TCK
P0.2/PLAO[8]/TDI
P0.1/PLAI[9]/TDO
P0.0/nTRST/ADCBUSY/PLAI[8]/BM
TMS
RTCK
XCLKO
XCLKI
P
0
.6
/M
IS
O
/S
C
L
1
/P
L
A
I[
2
]
P
0
.7
/M
O
S
I/
S
D
A
1
/P
L
A
O
[0
]
P
1
.0
/S
P
IC
L
K
/P
W
M
0
/P
L
A
O
[1
]
D
G
N
D
IO
V
D
L
V
D
A
G
N
D
A
D
C
3
/C
M
P
1
A
D
C
2
/C
M
P
0
A
D
C
1
A
D
C
0
V
R
E
F
P
1
.3
/A
D
C
5
/I
R
Q
3
/P
L
A
I[
4
]
P
1
.2
/A
D
C
4
/I
R
Q
2
/P
L
A
I[
3
]/
E
C
L
K
R
S
T
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
ADuC7023
TOP VIEW
(Not to Scale)
NOTES
1. EXPOSED PAD. THE PADDLE NEEDS TO BE SOLDERED AND
EITHER CONNECTED TO AGND OR LEFT FLOATING.
P
1
.1
/S
S
/I
R
Q
1
/P
W
M
1
/P
L
A
O
[2
]/
T
1
P0.4/IRQ0/SCL0/PLAI[0]/CONVSTART
Figure 8. 32-Lead LFCSP Pin Configuration
ADuC7023
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
086
75-
1
09
1
A
B
C
D
E
F
A1
B1
C1
D1
E1
F1
A2
B2
C2
D2
E2
F2
A3
B3
C3
D3
E3
F3
A4
B4
C4
D4
E4
F4
A5
B5
C5
D5
E5
F5
A6
B6
C6
D6
E6
F6
23
4
BALL A1
CORNER
56
Figure 9. 36-Lead WLCSP Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
40-
LFCSP
32-
LFCSP
36-
WLCSP
Mnemonic
Description
0
N/A
Exposed Paddle
Exposed Pad. The paddle needs to be soldered and either connected to
AGND or left floating.
36
28
A4
ADC0
Single-Ended or Differential Analog Input 0.
37
29
B4
ADC1
Single-Ended or Differential Analog Input 1.
38
30
A5
ADC2/CMP0
Single-Ended or Differential Analog Input 2/Comparator Positive Input.
39
31
B5
ADC3/CMP1
Single-Ended or Differential Analog Input 3/Comparator Negative Input.
32
N/A
B2
P2.4/ADC9/PLAI[10]
General-Purpose Input and Output Port 2.4/ADC Single-Ended or Dif-
ferential Analog Input/Programmable Logic Array Input Element 10.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled.
Rev. E
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