參數(shù)資料
型號(hào)： EVAL-ADUC7023QSPZ1
廠商： Analog Devices Inc
文件頁數(shù)： 35/96頁
文件大小： 0K
描述： BOARD EVAL FOR ADUC7023
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC7023
所含物品： 板
ADuC7023
Data Sheet
| Page 40 of 96
Code
Command
Description
0x0D
Reserved
Reserved.
0x0E
Reserved
Reserved.
0x0F
Ping
No operation; interrupt generated.
1
The FEECON register always reads 0x07 immediately after execution of any of these commands.
FEEDAT Register
Name:
FEEDAT
Address:
0xFFFFF80C
Default value: 0xXXXX
Access:
Read/write
Function:
FEEDAT is a 16-bit data register.
FEEADR Register
Name:
FEEADR
Address:
0xFFFFF810
Default value: 0x0000
Access:
Read/write
Function:
FEEADR is another 16-bit address register.
FEESIGN Register
Name:
FEESIGN
Address:
0xFFFFF818
Default value: 0xFFFFFF
Access:
Read
Function:
FEESIGN is a 24-bit code signature.
FEEPRO Register
Name:
FEEPRO
Address:
0xFFFFF81C
Default value: 0x00000000
Access:
Read/write
Function:
FEEPRO MMR provides protection following a
subsequent reset of the MMR. It requires a
software key (see Table 34).
FEEHIDE Register
Name:
FEEHIDE
Address:
0xFFFFF820
Default value: 0xFFFFFFFF
Access:
Read/write
Function:
FEEHIDE MMR provides immediate
protection. It does not require any software
key. The protection settings in FEEHIDE are
cleared by a reset (see Table 34).
Table 34. FEEPRO and FEEHIDE MMR Bit Designations
Bit
Description
31
Read protection.
This bit is cleared by the user to protect the code
This bit is set by the user to allow reading the code.
30 to 0
Write protection for Page 123 to Page 120, Page 119 to
Page 116, and Page 0 to Page 3.
This bit is cleared by the user to protect the pages in
writing.
This bit is set by the user to allow writing the pages.
Command Sequence for Executing a Mass Erase
FEEDAT = 0x3CFF;
FEEADR = 0xFFC3;
FEEMOD = FEEMOD|0x8;
//Erase key enable
FEECON = 0x06;
//Mass erase
command
Rev. E
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