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參數(shù)資料
| 型號： | EVAL-ADUC7023QSPZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 43/96頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADUC7023 |
| 標準包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC7023 |
| 所含物品： | 板 |
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ADuC7023
Data Sheet
| Page 48 of 96
OSCILLATOR AND PLL—POWER CONTROL
Clocking System
Each ADuC7023 integrates a 32.768 kHz ± 3% oscillator, a clock
divider, and a PLL. The PLL locks onto a multiple (1275) of the
internal oscillator or an external 32.768 kHz crystal to provide a
stable 41.78 MHz clock (UCLK) for the system. To allow power
saving, the core can operate at this frequency, or at binary
submultiples of it. The actual core operating frequency, UCLK/2CD,
is referred to as HCLK. The default core clock is the PLL clock
divided by 8 (CD = 3) or 5.22 MHz. The core clock frequency
can also come from an external clock on the ECLK pin as
described in Figure 36.
08675-
030
*32.768kHz ±3%
AT POWER UP
41.78MHz
OCLK 32.768kHz
WATCHDOG
TIMER
INTERNAL
32kHz*
OSCILLATOR
CRYSTAL
OSCILLATOR
TIMERS
MDCLK
HCLK
PLL
CORE
I2C
UCLK
ANALOG
PERIPHERALS
/2CD
CD
XCLKO
XCLKI
P1.2/XCLK
P1.2/ECLK
Figure 36. Clocking System
The selection of the clock source is in the PLLCON register. By
default, the part uses the internal oscillator feeding the PLL.
In noisy environments, noise can couple to the external crystal
pins, and PLL may quickly lose lock. A PLL interrupt is
provided in the interrupt controller. The core clock is immediately
halted, and this interrupt is only serviced when the lock is restored.
In case of crystal loss, use the watchdog timer. During
initialization, a test on the RSTSTA can determine if the reset
came from the watchdog timer.
Power Control System
A choice of operating modes is available on the ADuC7023.
Table 47 describes what part is powered on in the different
modes and indicates the power-up time.
Table 48 gives some typical values of the total current consumption
(analog + digital supply currents) in the different modes,
depending on the clock divider bits. The ADC is turned off.
Note that these values also include current consumption of the
regulator and other parts on the test board where these values
are measured.
Table 47. Operating Modes
Mode
Core
Peripherals
PLL
XTAL/T2/T3
IRQ0 to IRQ3
Start-Up/Power-On Time
Active
Yes
X
66 ms at CD = 0
Pause
X
230 ns at CD = 0; 3 s at CD = 7
Nap
X
283 ns at CD = 0; 3 s at CD = 7
Sleep
X
1.23 ms
Stop
X
1.45 ms
X = don’t care.
Table 48. Typical Current Consumption at 25°C in mA
PC[2:0]
Mode
CD = 0
CD = 1
CD = 2
CD = 3
CD = 4
CD = 5
CD = 6
CD = 7
000
Active
28
17
12
11
9.3
7.5
7.2
7
001
Pause
14
9
7.6
5.7
4.8
4.6
010
Nap
5
4.5
011
Sleep
0.23
100
Stop
0.23
Rev. E
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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