參數(shù)資料
型號： EVAL-ADUC7023QSPZ1
廠商： Analog Devices Inc
文件頁數(shù)： 41/96頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7023
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC7023
所含物品： 板
ADuC7023
Data Sheet
| Page 46 of 96
DACBKEY0 Register
Name:
DACBKEY0
Address:
0xFFFF0650
Default value:
0x0000
Access:
Write
DACBKEY1 Register
Name:
DACBKEY1
Address:
0xFFFF0658
Default value:
0x0000
Access:
Write
Table 44. DACBCFG Write Sequence
Name
Code
DACBKEY0
0x9A
DACBCFG
User value
DACBKEY1
0x0C
POWER SUPPLY MONITOR
The power supply monitor regulates the IOVDD supply on the
ADuC7023. It indicates when the IOVDD supply pin drops
below a supply trip point. The monitor function is controlled
via the PSMCON register. If enabled in the IRQEN or FIQEN
register, the monitor interrupts the core using the PSMI bit in
the PSMCON MMR. This bit is immediately cleared when
CMP goes high.
This monitor function allows the user to save working registers
to avoid possible data loss due to low supply or brownout
conditions. It also ensures that normal code execution does not
resume until a safe supply level has been established.
PSMCON Register
Name:
PSMCON
Address:
0xFFFF0440
Default value:
0x0008
Access:
Read/write
Table 45. PSMCON MMR Bit Descriptions
Bit
Name
Description
3
CMP
Comparator bit. This is a read-only bit that
directly reflects the state of the comparator.
Read 1 indicates the IOVDD supply is above its
selected trip point, or the PSM is in power-down
mode. Read 0 indicates the IOVDD supply is
below its selected trip point. This bit should be
set before leaving the interrupt service routine.
2
TP
Trip point selection bits.
0 = 2.79 V.
1 = reserved.
1
PSMEN
Power supply monitor enable bit.
This bit is set to 1 to enable the power supply
monitor circuit.
This bit is cleared to 0 to disable the power
supply monitor circuit.
0
PSMI
Power supply monitor interrupt bit. This bit is set
high by the MicroConverter once CMP goes low,
indicating low I/O supply. The PSMI bit can be
used to interrupt the processor. Once CMP
returns high, the PSMI bit can be cleared by
writing a 1 to this location. A 0 write has no
effect. There is no timeout delay; PSMI can be
immediately cleared once CMP goes high.
COMPARATOR
The ADuC7023 integrates voltage comparators. The positive
input is multiplexed with ADC2, and the negative input has two
options: ADC3 or DAC0. The output of the comparator can be
configured to generate a system interrupt, be routed directly to
the programmable logic array, start an ADC conversion, or be
on an external pin, COMPOUT, as shown in Figure 34.
08
675
-02
8
MUX
IRQ
MUX
DAC0
ADC2/CMP0
ADC3/CMP1
P0.5/COMPOUT
Figure 34. Comparator
Hysteresis
Figure 35 shows how the input offset voltage and hysteresis
terms are defined. Input offset voltage (VOS) is the difference
between the center of the hysteresis range and the ground level.
This can either be positive or negative. The hysteresis voltage
(VH) is the width of the hysteresis range.
08
67
5-
02
9
COMPOUT
CMP0
VH
VOS
Figure 35. Comparator Hysteresis Transfer Function
Rev. E
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