參數(shù)資料
型號(hào)： EVAL-ADUC7023QSPZ1
廠商： Analog Devices Inc
文件頁數(shù)： 21/96頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7023
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC7023
所含物品： 板
ADuC7023
Data Sheet
| Page 28 of 96
Table 21. PWM Base Address = 0xFFFF0F80
Address
Name
Byte
Access Type
Default Value
Description
0x0F80
PWMCON1
2
R/W
0x0012
PWM Control Register 1. See the Pulse-Width Modulator section
for full details.
0x0F84
PWM0COM0
2
R/W
0x0000
Compare Register 0 for PWM Output 0 and PWM Output 1.
0x0F88
PWM0COM1
2
R/W
0x0000
Compare Register 1 for PWM Output 0 and PWM Output 1.
0x0F8C
PWM0COM2
2
R/W
0x0000
Compare Register 2 for PWM Output 0 and PWM Output 1.
0x0F90
PWM0LEN
2
R/W
0x0000
Frequency control for PWM Output 0 and PWM Output 1.
0x0F94
PWM1COM0
2
R/W
0x0000
Compare Register 0 for PWM Output 2 and PWM Output 3.
0x0F98
PWM1COM1
2
R/W
0x0000
Compare Register 1 for PWM Output 2 and PWM Output 3.
0x0F9C
PWM1COM2
2
R/W
0x0000
Compare Register 2 for PWM Output 2 and PWM Output 3.
0x0FA0
PWM1LEN
2
R/W
0x0000
Frequency control for PWM Output 2 and PWM Output 3.
0x0FA4
PWM2COM0
2
R/W
0x0000
Compare Register 0 for PWM Output 4 and PWM Output 5.
0x0FA8
PWM2COM1
2
R/W
0x0000
Compare Register 1 for PWM Output 4 and PWM Output 5.
0x0FB8
PWMCLRI
2
W
0x0000
PWM interrupt clear register. Writing any value to this register
clears a PWM interrupt source.
Table 22. GPIO Base Address = 0xFFFFF400
Address
Name
Byte
Access Type
Default Value
Description
0xF400
GP0CON
4
R/W
0x00001111
GPIO Port0 control MMR.
0xF404
GP1CON
4
R/W
0x00000000
GPIO Port1 control MMR.
0xF408
GP2CON
4
R/W
0x00000000
GPIO Port2 control MMR.
0xF420
GP0DAT
4
R/W
0x000000XX
GPIO Port0 data control MMR.
0xF424
GP0SET
4
W
0x000000XX
GPIO Port0 data set MMR.
0xF428
GP0CLR
4
W
0x000000XX
GPIO Port0 data clear MMR.
0xF42C
GP0PAR
4
R/W
0x22220000
GPIO Port0 pull-up disable MMR.
0xF430
GP1DAT
4
R/W
0x000000XX
GPIO Port1 data control MMR.
0xF434
GP1SET
4
W
0x000000XX
GPIO Port1 data set MMR.
0xF438
GP1CLR
4
W
0x000000XX
GPIO Port1 data clear MMR.
0xF43C
GP1PAR
4
R/W
0x22000022
GPIO Port1 pull-up disable MMR.
0xF440
GP2DAT
4
R/W
0x000000XX
GPIO Port2 data control MMR.
0xF444
GP2SET
4
W
0x000000XX
GPIO Port2 data set MMR.
0xF448
GP2CLR
4
W
0x000000XX
GPIO Port2 data clear MMR.
0xF44C
GP2PAR
4
R/W
0x00000000
GPIO Port2 pull-up disable MMR.
Table 23. Flash/EE Base Address = 0xFFFFF800
Address
Name
Byte
Access Type
Default Value
Description
0xF800
FEESTA
1
R
0x20
Flash/EE status MMR.
0xF804
FEEMOD
2
R/W
0x0000
Flash/EE control MMR.
0xF808
FEECON
1
R/W
0x07
Flash/EE control MMR.
0xF80C
FEEDAT
2
R/W
0xXXXX
Flash/EE data MMR.
0xF810
FEEADR
2
R/W
0x0000
Flash/EE address MMR.
0xF818
FEESIGN
3
R
0xFFFFFF
Flash/EE LFSR MMR.
0xF81C
FEEPRO
4
R/W
0x00000000
Flash/EE protection MMR.
0xF820
FEEHIDE
4
R/W
0xFFFFFFFF
Flash/EE protection MMR.
Rev. E
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