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| 型號： | EVAL-ADUC7023QSPZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/96頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADUC7023 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC7023 |
| 所含物品： | 板 |
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Data Sheet
ADuC7023
| Page 15 of 96
Pin No.
40-
LFCSP
32-
LFCSP
36-
WLCSP
Mnemonic
Description
31
N/A
A1
P2.3/ADC8/PLAO[7]
General-Purpose Input and Output Port 2.3/ADC Single-Ended or
Differential Analog Input 8/Programmable Logic Array Output Element 7.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled. When used as ADC input, pull-up resistor should be
disabled manually.
30
N/A
B1
P2.2/ADC7/SYNC/PLAO[6]
General-Purpose Input and Output Port 2.2/ADC Single-Ended or
Differential Analog Input 7/PWM Sync/Programmable Logic Array Output
Element 6. By default, this pin is configured as a digital input with a weak
pull-up resistor enabled. When used as ADC input, pull-up resistor should
be disabled manually.
8
N/A
E6
P2.0/ADC12/PWM4/PLAI[7]
General-Purpose Input and Output Port 2.0/ADC Single-Ended or
Differential Analog Input 12/PWM Output 4/Programmable Logic Array Input
Element 7. By default, this pin is configured as a digital input with a weak pull-
up resistor enabled. When used as an ADC input, it is not possible to
disable the internal pull-up resister. This means that this pin has a higher
leakage current value than other analog input pins.
2
C4
GNDREF
Ground Voltage Reference for the ADC. For optimal performance, the
analog power supply should be separated from DGND.
3
C5
DAC0
DAC0 Voltage Output or ADC Input.
4
C6
DAC1
DAC1 Voltage Output or ADC Input.
5
D5
DAC2
DAC2 Voltage Output
6
D6
DAC3
DAC3 Voltage Output
24
20
D2
TMS
Test Mode Select, JTAG Test Port Input. Debug and download access.
This pin has an internal pull-up resistor to IOVDD. In some cases an external
pull-up resistor is also required to ensure the part does not enter an
erroneous state.
25
21
D1
P0.0/nTRST/ADCBUSY/PLAI[8]/BM
This is a multifunction pin as follows:
General-Purpose Input and Output Port 0.0. By default, this pin is
configured as GPIO.
JTAG Reset Input. Debug and download access. If this pin is held low, JTAG
access is not possible because the JTAG interface is held in reset and
P0.1/P0.2/P0.3 are configured as GPIO pins.
ADC Busy Signal.
Programmable Logic Array Input Element 8.
Boot Mode Entry Pin. The ADuC7023 enters I2C download mode if BM is
low at reset with a flash address 0x80014 = 0xFFFFFFFFF. The ADuC7023
executes code if BM is pulled high at reset or if BM is low at reset with a
flash address 0x80014 not equal to 0xFFFFFFFFF.
26
22
C1
P0.1/PLAI[9]/TDO
The default value of this pin depends on the level of P0.0/BM. If P0.0/
BM = 0, this pin defaults to a general purpose input. If P0.0/BM = 1, this
pin defaults to a JTAG test data output pin. This is a multifunction pin as
follows:
General-Purpose Input and Output Port 0.1.
Programmable Logic Array Input Element 9.
Test Data Out, JTAG Test Port Output. Debug and download access. When
debugging the part via JTAG, this pin must not be toggled by user code,
and the GP0CON/GP0DAT register bits affecting this pin can not be
changed.
27
23
C2
P0.2/PLAO[8]/TDI
The default value of this pin depends on the level of P0.0/BM. If P0.0/
BM = 0, this pin defaults to a general purpose input. If P0.0/BM = 1, this pin
defaults to a JTAG test data input pin. This is a multifunction pin as follows:
General-Purpose Input and Output Port 0.2.
Programmable Logic Array Output Element 8.
Test Data In, JTAG Test Port Input. Debug and download access. When
debugging the part via JTAG, this pin must not be toggled by user code,
and the GP0CON/GP0DAT register bits affecting this pin must not be
changed.
Rev. E
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