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參數(shù)資料
| 型號： | AD6623ASZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TSP 4CHAN 104MSPS 128MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 傳輸信息處理器 |
| 接口： | 串行 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-MQFP（14x20） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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REV. A
AD6623
–17–
OVERVIEW OF THE RCF BLOCKS
The Serial Port passes data to the RCF with the appropriate format
and bit precision for each RCF configuration, see Figure 17. The
data may be modulated vectors or unmodulated bits. I and Q vectors
are sent directly to the Interpolating Fir Filter. Unmodulated
bits may be sent to the PSK Modulator, the Interpolating MSK
Modulator, or the Interpolating QPSK Modulator. The PSK
Modulator produces unfiltered I and Q vectors at the symbol rate
which are then passed through the Interpolating FIR Filter. The
Interpolating MSK Modulator and the Interpolating QPSK
Modulator produce oversampled, pulse-shaped vectors directly
without employing the Interpolating FIR Filter. When possible,
the MSK and QPSK modulators are recommended for increased
throughput and decreased power consumption compared to
Interpolating FIR Filter. In addition, the Interpolating MSK
Modulator can realize filters with nonlinear inter-symbol inter-
ference, achieving excellent accuracy for GMSK applications.
After interpolation, an optional Allpass Phase Equalizer (APE)
can be inserted into the signal path. The APE can realize any real,
stable, two-pole, two-zero all-pass filter at the RCF’s interpolated
rate. This is especially useful to precompensate for nonlinear phase
responses of receive filters in terminals, as specified by IS-95.
When active, the APE utilizes shared hardware with the interpo-
lating modulators and filter, which may reduce the allowed RCF
throughput, inter-symbol interference, or both. See Figure 18.
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23
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18
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16
15
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11
10
9876543210
BIT
< MSB, I, LSB >
< MSB, Q, LSB >
FIR
23
22
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20
19
18
17
16
15
14
13
12
11
10
9876
543210
BIT
< MSB, I, LSB >
< MSB, Q, LSB >
COMPACT FIR
15
14
13
12
11
10
9876543210
BIT
< MSB, I, LSB >
< MSB, Q, LSB >
COMPACT FIR
43210
BIT
MS
D1
D2
D0
8PSK
43210
BIT
SERIAL SYNC
MSX
D1
D0QPSK
RAMP
43210
BIT
MSXX
D0
MSK/GSM
210
BIT
0D1D0
8PSK
10
BIT
D1
D0
QPSK
0BIT
D0
MSK/GSM
These three formats are
available only when SERIAL
TIME SLOT SYNC ENABLE
cont. reg. 0xn16:2 = 1 and
ignored in FIR Mode
These three formats are
available only when SERIAL
TIME SLOT SYNC ENABLE
cont. reg. 0xn16:2 = 0 and
ignored in FIR Mode
M = mode bit. If M = 0, then the MSB of 3-bit mode select word at 0xn0C:6 is set to 0 (this is also called MODE 0). If M = 1, then the MSB is set to 1 and this is
MODE 1. Mode allows quick format changes via the serial port, for example, 010 = GMSK and 110 = 3pi/8PSK. The value m should be held for the duration of the
time slot since the value of m will only be updated after the RCF Scale Holdoff Counter reaches a value of 1 (see below).
S = serial time slot sync bit. If S = 0, then no sync is generated. If S = 1, a “Serial Time Slot Sync” occurs that loads the RCF Scale Hold-off Counter with a user
programmed value and commences a backwards count of CLK cycles. When the counter reaches one, an automatic sequence occurs as follows: Power Ramp
Down occurs, m (above) is updated, serial input is suspended for a REST or QUIET time and any control register with a 2 superscript is updated. After REST, the
serial input becomes active and the power level is ramped up to the Fine Scale multiplier value or any lesser power level. Ramp enable bit, 0xn16:0, must be set
to logic 1 for the ramp functions to occur. See the RCF Power Ramping and Time Slot Synchronization sections for more detail.
X = don’t care
D = payload data bit
Important notes: The sync pulse, s, should be held at Logic 1 for only one serial frame since every frame with Logic 1 in the s position will cause the RCF Scale Hold-off
Counter to reload its beginning count and begin counting again.The RCF Scale Hold-off Counter counts master CLK cycles. The REST time period is a programmable 5-bit
value that counts interpolated RCF output samples before resuming serial input to the channel. The succeeding actions of any hold-off counter in the AD6623 can be defeat-
ed by setting its count value to 0.
Figure 17. Data Formats Supported by the AD6623 when SCLK Master (SCS = 0), and SFDO Set for Frame Request (SFE = 0)
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| AD6623BC/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6623PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6623S/PCB | 制造商:Analog Devices 功能描述:4-CH, 104 MSPS DGTL TRANSMIT SGNL PROCESSOR (TSP) 28SOIC - Bulk |
| AD6624 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
| AD6624A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
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