NRCFTAP FIR FILTER h[n] L
參數(shù)資料
型號(hào)： AD6623ASZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/48頁(yè)
文件大小： 0K
描述： IC TSP 4CHAN 104MSPS 128MQFP
標(biāo)準(zhǔn)包裝： 1
應(yīng)用： 傳輸信息處理器
接口： 串行
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-MQFP（14x20）
包裝： 托盤
安裝類型： 表面貼裝
REV. A
AD6623
–19–
NRCFTAP
FIR FILTER
h[n]
LRCF
fIN
LRCF
b
a
c
fIN
LRCF
Figure 20. RCF Interpolation
cn
h n
b n
k
N RCF
[] =
[]
∑
×
[]
=
k
0
–
1
(5)
This difference equation can be described by the transfer function
from point ‘b’ to ‘c’ as:
Hz
h n
z
bc
k
N RCF
()
–
=
[]
∑
×
= 0
1
(6)
The actual implementation of this filter uses a polyphase decom-
position to skip the multiply-accumulates when b[n–k] is zero.
Compared to the diagram above, this implementation has the benefits
of reducing by a factor of LRCF both the time needed to calculate
an output and the required data memory (DMEM). The price of
these benefits is that the user must place the coefficients into the coefficient
memory (CMEM) indexed by the interpolation phase. The process of
selecting the coefficients and placing them into the CMEM is broken
into three steps shown below.
The FIR accepts two’s complement I and Q samples from the serial
port with a fixed-point resolution of 16 bits each. When the serial port
provides data with less precision, the LSBs are padded with zeroes.
The Data-Mem stores the most recent 16 I and Q pairs for a total
of 32 words. The size of the Data-Mem limits the RCF impulse
response to 16
LRCF output samples. When the data words from
the Serial Port have fewer than 16 bits, the LSBs are padded with
zeroes. The Data-Mem can be accessed through the Microport
from 0x20 to 0x5F above the processing channel’s base internal
address, while the channel’s Prog bit is set (external address 4).
In order to avoid start-up transients, the Data-Mem should be
cleared before operation. The Prog bit must then be reset to
enable normal operation.
The Coef-Mem stores up to 256 16-bit filter coefficients. The Coef-
Mem can be accessed through the Microport from 0x800 to 0x8FF
above the processing channel’s base internal address, while the channel’s
Prog bit is set (external address 4). For AD6622 compatibility, the
lower 128 words are also mirrored from 0x080 to 0x0FF above the
processing channel’s base internal address, while the Prog bit is set.
There is a single Multiply-Accumulator (MAC) on which both the
I and Q operations must be interleaved. Two CLK cycles are required
for the MAC to multiply each coefficient by an I and Q pair. The
MAC is also used for four additional CLK cycles if the All-pass
Phase Equalizer is active.
The size of the Data-Mem and Coef-Mem combined with the
speed of the MAC determine the total number of the taps per
phase (TRCF) that may be calculated. TRCF is the number of
RCF input samples that influence each RCF output sample.
The maximum available TRCF is calculated by the equation below.
T
least of
floor
L
floor
f
APE
RCF
CLK
SDFO
≤
×
16
256
2
,,
–
(7)
Where APE = 1 (allpass phase equalizer enabled) or 0 (allpass
phase equalizer disabled) and fSDFO = [Output Data Rate/Total
Interpolation Rate] in Hz. “floor()” indicates that the value
within the parenthesis should be reduced to the lowest integer,
e.g., floor(9.9999) = 9.
The impulse response length at the output of the RCF is determined
by the product of the number of interfering input samples (TRCF)
and the RCF interpolation factor (LRCF), as shown by equation (8)
below. The values of NRCF and TRCF are programmed into control
registers. LRCF is not a control register, but NRCF and TRCF must
be set so that LRCF is an integer. If the integer interpolation by the
RCF results in an inconvenient sample rate at the output of the
RCF, the desired output rate can usually be achieved by selecting
non-integer interpolation in the resampling CIC
2 filter.
NT
L
RCF
=×
(8)
相關(guān)PDF資料
PDF描述
AD6641BCPZRL7-500 IC IF RCVR 11BIT 200MSPS 56LFCSP
AD664BJ IC DAC 12BIT QUAD MONO 44-JLCC
AD667BD IC DAC 12BIT W/BUFF LTCH 28-CDIP
AD669BN IC DAC 16BIT MONO VREF 28-DIP
AD693AE IC SGNL COND 4-20MA TX 20-CLCC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD6623BC/PCB 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 104 MSPS Digital Transmit Signal Processor TSP
AD6623PCB 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 104 MSPS Digital Transmit Signal Processor TSP
AD6623S/PCB 制造商:Analog Devices 功能描述:4-CH, 104 MSPS DGTL TRANSMIT SGNL PROCESSOR (TSP) 28SOIC - Bulk
AD6624 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP)
AD6624A 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*