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參數(shù)資料
| 型號(hào)： | AD6623ASZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TSP 4CHAN 104MSPS 128MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 傳輸信息處理器 |
| 接口： | 串行 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-MQFP（14x20） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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REV. A
AD6623
–30–
Start
Refers to the start-up of an individual channel, chip, or multiple
chips. If a channel is not used, it should be put in the Sleep Mode to
reduce power dissipation. Following a hard reset (low pulse on
the AD6623 RESET pin), all channels are placed in the Sleep Mode.
Start With No Sync
If no synchronization is needed to start multiple channels or multiple
AD6623s, the following method should be used to initialize the
device.
1. To program a channel, it must first be set to the Program
Mode (bit high) and Sleep Mode (bit high) (Ext Address 4).
The Program Mode allows programming of data memory and
coefficient memory (all other registers are programmable
whether in Program Mode or not). Since no synchronization
is used, all Sync bits are set low (External Address 5). All appro-
priate control and memory registers (filter) are then loaded. The
Start Update Hold-Off Counter (0xn00) should be set to 0.
2. Set the appropriate program and sleep bits low (Ext Address 4).
This enables the channel. The channel must have Program
and Sleep Mode low to activate a channel.
Start with SoftSync
The AD6623 includes the ability to synchronize channels or chips
under microprocessor control. One action to synchronize is the
start of channels or chips. The Start Update Hold-Off Counter
(0xn00) in conjunction with the Start bit and Sync bit (Ext
Address 5) allow this synchronization. Basically the Start Update
Hold-Off Counter delays the Start of a channel(s) by its value
(number of AD6623 CLKs). The following method is used to syn-
chronize the start of multiple channels via microprocessor control.
1. Set the appropriate channels to sleep mode (a hard reset to the
AD6623 Reset pin brings all four channels up in Sleep Mode).
2. Write the Start Update Hold-Off Counter(s) (0xn00) to the
appropriate value (greater than 1 and less than 2
16–1). If the
chip(s) is not initialized, all other registers should be loaded
at this step.
3. Write the Start bit and the Syncx(s) bit high (Ext Address 5).
4. This starts the Start Update Hold-Off Counter counting down.
The counter is clocked with the AD6623 CLK signal. When it
reaches a count of one the sleep bit of the appropriate channel(s)
is set low to activate the channel(s).
Start with Pin Sync
Four hardware sync pins are available on the AD6623 to pro-
vide the most accurate synchronization, especially between
multiple AD6623s. Synchronization of start with an external
signal is accomplished with the following method.
1. Set the appropriate channels to sleep mode (a hard reset to the
AD6623 Reset pin brings all four channels up in sleep mode).
2. Write the Start Update Hold-Off Counter(s) (0xn00) to the
appropriate value (greater than 1 and less than 2
16–1). If the
chip(s) is not initialized, all other registers should be loaded
at this step.
3. Set the Start on Pin Sync bit and the appropriate Sync Pin
Enable high (0xn01).
4. When the Sync pin is sampled high by the AD6623 CLK this
enables the count down of the Start Update Hold-Off Counter.
The counter is clocked with the AD6623 CLK signal. When it
reaches a count of one the sleep bit of the appropriate channel(s)
is set low to activate the channel(s).
Hop
A jump from one NCO frequency to a new NCO frequency. This
change in frequency can be synchronized via microprocessor
control or an external Sync signal as described below.
To set the NCO frequency without synchronization the following
method should be used.
Set Frequency No Hop
1. Set the NCO Frequency Hold-Off Counter to 0.
2. Load the appropriate NCO frequency. The new frequency
will be immediately loaded to the NCO.
Hop with SoftSync
The AD6623 includes the ability to synchronize a change in NCO
frequency of multiple channels or chips under microprocessor
control. The NCO Frequency Hold-Off Counter (0xn03) in
conjunction with the Hop bit and the Sync bit (Ext Address 5)
allow this synchronization. Basically the NCO Frequency Hold-Off
counter delays the new frequency from being loaded into the NCO
by its value (number of AD6623 CLKs). The following method
is used to synchronize a hop in frequency of multiple channels
via microprocessor control.
1. Write the NCO Frequency Hold-Off (0xn03) counter to the
appropriate value (> 1 and < 2
16–1).
2. Write the NCO Frequency register(s) to the new desired
frequency.
3. Write the Hop bit and the Sync(s) bit high (Ext Address 5).
4. This starts the NCO Frequency Hold-Off counter counting
down. The counter is clocked with the AD6623 CLK signal.
When it reaches a count of one the new frequency is loaded
into the NCO.
Hop with Pin Sync
Four hardware Sync pins are available on the AD6623 to pro-
vide the most accurate synchronization, especially between
multiple AD6623s. Synchronization of hopping to a new NCO
frequency with an external signal is accomplished with the fol-
lowing method.
1. Write the NCO Frequency Hold-Off Counter(s) (0xn03) to
the appropriate value (greater than 1 and less than 2
16–1).
2. Write the NCO Frequency register(s) to the new desired
frequency.
3. Set the Hop on Pin Sync bit and the appropriate Sync pin
Enable high (0xn01).
4. When the Sync pin is sampled high by the AD6623 CLK
this enables the count down of the NCO Frequency Hold-Off
Counter. The counter is clocked with the AD6623 CLK signal.
When it reaches a count of one the new frequency is loaded
into the NCO.
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