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參數(shù)資料
| 型號(hào)： | AD6623ASZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 40/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TSP 4CHAN 104MSPS 128MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 傳輸信息處理器 |
| 接口： | 串行 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-MQFP（14x20） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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REV. A
AD6623
–45–
The FIR filter coefficients for the reference filter are:
–181
–101
24803
2420
–816
–4461
14446
1729
–1084
–5366
1588
–209
1588
–5366
–1084
1729
14446
–4461
–816
2420
24803
–101
–181
Start Sync Control Register (0xn00, Bits 17:16)
The settings in this register must be the same for each pair of
processing channels.
Start Holdoff Counter (0xn00, Bits 15:0)
The secondary channel of each processing pair needs to be
configured such that it begins processing 180 degrees out of phase
with the primary channel. The Start Holdoff Counter (SHC) of
the secondary channel is set to the value of the primary channel
plus LTOT/2, where LTOT is the overall channel interpolation.
SCC
L
ndChannel
stChannel
TOT
21
2
=+
(34)
For example, in the case of LTOT = 48, the primary channel of
each processing is set to two, while the secondary channel’s
Start Holdoff Counter is set to twenty-six.
NCO Frequency Registers (0xn02, Bits 31:0)
Each pair of processing channels must be assigned the same
NCO Frequency Register values.
NCO Frequency Holdoff Counter (0xn03, Bits 15:0)
Each pair of processing channels must be assigned the same
NCO Holdoff Counter value.
NCO Phase Offset Register (0xn04, Bits 15:0)
The NCO of the secondary channel must have its initial phase
set such that, when it begins processing, its phase is equal to
that of the primary channel’s phase. The equation is given by:
NCOPhaseOffset
round frac
Lf
f
TOT
NCO
SAMP
=
2
16
(35)
where
round() returns the nearest integer of its argument,
frac() returns the fractional part of its argument,
fNCO is the desired NCO frequency, and
fSAMP is the desire output sample rate.
NCO Phase Offset Update Holdoff (0xn05, Bits 15:0)
Each pair of processing channels must be assigned the same
NCO Phase Offset Update Holdoff value.
CIC Scale (0xn06, Bits 4:0)
Each pair of processing channels must use a value of seventeen
for this register (SCIC = 12).
rCIC2 Decimation-1 (0xn07, Bits 8:0)
Each pair of processing channels must use a value of zero for
this register (rCIC2 decimation = 0).
rCIC2 Interpolation-1 (0xn08, Bits 7:0)
Each pair of processing channels must use a value of zero for
this register (rCIC2 interpolation = 0).
CIC5 Interpolation-1 (0xn09, Bits 7:0)
Each pair of processing channels must use a value of seven for
this register (CIC5 interpolation = 7).
RCF Number of Taps-1 (0xnA0, Bits 7:0)
Each pair of processing channels must use a value of twenty-
three for this register (NRCF-1 = 23).
RCF Coefficient Offset (0xn0B, Bits 7:0)
Each processing channel must specify the offset of the address
where its coefficients begin (typically zero).
RCF Mode (0xn0C, Bits 9:4)
Each pair of processing channels must set all these bits to zero.
RCF Mode (0xn0C, Bits 3:0)
Each pair of processing channels must be assigned the same
number of taps per phase which in this case is four.
Serial Data Frame Input Select (0xn16, Bits 7:6)
The secondary channel of each processing pair needs to be
configured such that it begins processing data after the primary
channel’s Frame end. This is done by setting the Serial Data
Frame Input Select bits high (Bits 7:6 = 11).
Serial Data Frame Output Select (0xn16, Bits 5)
The primary channel of each processing pair needs to be
configured such that it is configured for Serial Data Frame
Request (Bit 5 = 0).
Serial Clock Slave (0xn16, Bits 4)
Each pair of processing channels must be configured in Master
mode (Bit 4 = 0).
Performance
The filter performance of the AD6623’s dual-channel processing
approach is shown in Figure 45. This filter uses 24 taps, with
RCF interpolation of 6, CIC5 interpolation of 8, and rCIC2
interpolation and decimation of 1 and 1, respectively. The near
rejection at 5 MHz is 65 dBc, and rejection at 10 MHz is 80 dBc,
with a passband ripple of 0.25 dB. The register settings implement-
ing this filter are outlined in the AD6623 Register Configuration
section of this technical note.
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|---|---|
| AD6623BC/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6623PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6623S/PCB | 制造商:Analog Devices 功能描述:4-CH, 104 MSPS DGTL TRANSMIT SGNL PROCESSOR (TSP) 28SOIC - Bulk |
| AD6624 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
| AD6624A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
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