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參數(shù)資料
| 型號(hào)： | AD6623ASZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TSP 4CHAN 104MSPS 128MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 傳輸信息處理器 |
| 接口： | 串行 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-MQFP（14x20） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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REV. A
AD6623
–32–
9. This starts the Fine Scale Hold-Off Counter counting down.
The counter is clocked with the AD6623 CLK signal. When
it reaches a count of one, the ramp will commence from the
last coefficient until it reaches the first coefficient of the
specified ramp length. If a Rest has been programmed, Rest
will commence for the programmed length and then the ramp
will begin again at the first coefficient and ending at the last
coefficient in the RMEM (ramp memory).
Time Slot with Pin Sync
The procedure for using the hardware synchronizing pins
(SYNC0, 1, 2, and 3) to engage the Time Slot function is very
similar to the Soft Sync. So for this case, only the differences
between the two methods will be noted. It will be helpful to
examine the Hardware and Software Sync Control Block Diagram,
Figure 37, in order to visualize the process.
Hardware sync pins, (SYNC0, 1, 2, and 3), are all capable of
loading the Fine Scale Hold-Off Counters that trigger the ramp
function of any channel. The SYNC pin labels do not signify
attachment to specific channels, but conversely, each SYNC pin
is routed directly or indirectly to every channel. The task that
the user faces is to see that the sync signal is properly routed
and selected. The Time Slot Sync multiplexer seen in Figure 37
is used to select a hardware pin sync signal. SYNC1, 2, and 3
are directly routed to the multiplexer, whereas SYNC0 is routed
through two AND gates before it reaches the multiplexer. The
AND gates duplicate the AD6622 single sync pin function to
allow pin compatibility.
*SYNC0 is routed in parallel to both the Beam and Time Slot multiplexers and it
is a “shared” signal after is has been enabled at 0x001:6.
To use SYNC1, 2, or 3, simply set the select “l(fā)ines” according
to the Channel Register address (0xn0F:16-17) for the desired
sync signal. Attach a sync signal source to the package pin.
When it is time to sync, assert a Logic high (minimum 1 CLK
period +2 ns duration) and return to Logic 0. This loads the
Fine Scale Hold-Off Counter and a countdown commences.
Holding a logic high at the chosen sync input pin longer than
needed will result in additional delay as the Scale Hold-Off
Counter is continually loaded with the same beginning count.
From the Block Diagram, Figure 37, it can be seen (note the
OR gates at the output of each multiplexer) that a software sync
can also be used in conjunction with a hardware sync without
any modification to the hardware setup.
SYNC0 is selected at the Time Slot multiplexer using the same
select “l(fā)ines” at 0xn0F:16-17 as for SYNC 1, 2, and 3; however,
two additional “masking” registers must be dealt with to get
SYNC0 routed to the Time Slot Sync multiplexer. First,
SYNC0 must be enabled to enter the desired channel(s) using
Common Function Register address 0x001:3-0 (Logic High =
selected). Secondly, once the channel(s) is/are selected, then the
Beam
* multiplexer must be selected as the destination for Sync0
by setting 0x001:6 to Logic High.
Once the pin sync signals have been connected, routed and
selected, the procedure for triggering a Time Slot or Ramp
sequence is nearly identical as outlined for a soft sync except for
Step 8. The user should substitute the pin-sync procedure in
place of the soft sync method.
TO FINE
SCALE HOLDOFF
COUNTER
TO PHASE
HOLDOFF
COUNTER
TO HOP
HOLDOFF
COUNTER
TO START
HOLDOFF
COUNTER
SOFTWARE BEAM/TIME
SLOT SYNC 0x001:6
SOFTWARE HOP
SYNC 0x001:5
SOFTWARE START
SYNC 0x001:4
CHA. A
START
SYNC
MUX
SELECT LINES FROM
CONTROL REGISTER
CHA. A
HOP
SYNC
MUX
SELECT LINES FROM
CONTROL REGISTER
CHA. A
PHASE
OR BEAM
SYNC
MUX
SELECT LINES FROM
CONTROL REGISTER
CHA. A
TIME
SLOT
SYNC
SELECT LINES FROM
CONTROL REGISTER
0x001:4 START SYNC
SYNC0
SYNC1
SYNC2
SYNC3
0x100:17
0x100:16
0x001:5 HOP SYNC
SYNC0
SYNC1
SYNC2
SYNC3
0x103:17
0x103:16
0x001:6 BEAM SYNC
SYNC0
SYNC1
SYNC2
SYNC3
0x105:17
0x105:16
SYNC0
SYNC1
SYNC2
SYNC3
0x10F:17
0x10F:16
CHANNEL A
SYNC0
ENABLE
0x001:0
CHANNEL B
SYNC0
ENABLE
0x001:1
CHANNEL C
SYNC0
ENABLE
0x001:2
CHANNEL D
SYNC0
ENABLE
0x001:3
TO CHANNEL A
MULTIPLEXERS
TO CHANNEL B
MULTIPLEXERS
TO CHANNEL C
MULTIPLEXERS
TO CHANNEL D
MULTIPLEXERS
HARDWARE
SYNC PINS
SYNC3 PIN
SYNC2 PIN
SYNC1 PIN
SYNC0 PIN*
SYNC 1, 2, AND 3
ROUTE DIRECTLY TO
EACH CHANNEL
MUX FOR EVERY
SYNC FUNCTION
*HARDWARE SYNC 0 IS CONFIGURED TO MATCH THE SYNC FUNCTION OF THE AD6622 FOR PIN COMPATIBILITY
Figure 37. Block Diagram of Hardware and Software Sync Control for One AD6623 Sync Channel
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