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參數(shù)資料
| 型號(hào)： | AD6623ASZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TSP 4CHAN 104MSPS 128MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 傳輸信息處理器 |
| 接口： | 串行 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-MQFP（14x20） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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REV. A
AD6623
–23–
Logic 1. This extends the maximum ramp length to 128 coeffi-
cients. Although the ramp is limited in length, its time duration
is a function of the output sample rate of the RCF multiplied
by the ramp length. Ramp duration is twice as long with Ramp
Interpolation enabled than when it is not enabled.
The channel’s Ramp Enable bit at control register address
0xn16: bit 0, must be set to Logic 1 or else the ramp function
will be bypassed and the RCF output data is passed unaltered to
the CIC interpolation stages. When in use, the maximum signal
gain is dependent on what value is stored in the last valid
RMEM (ramp memory) location. RMEM words are 14-bits
with a range of [0-1).
When the ramp is triggered, the following sequence occurs (see
Figures 26 and 27): RAMP-DOWN beginning at the last coefficient
of the specified ramp length and proceeding, sample-by-sample,
to the first coefficient. Next, a REST or quiet period (from
0 to 32 RCF output samples duration) occurs. During this
time, the Mode bit (as shown in Figure 17, AD6623 Data Format
and Bit Definition chart) is updated, input sampling is halted and
any control register with a superscript 2 is updated. Modulator
configurations can be updated while the ramp is “quiet” allowing
for GSM and EDGE timeslots to be multiplexed without resetting
or reconfiguring the channel. Lastly, RAMP-UP occurs beginning
at the first coefficient and ending at the last coefficient of the
specified length. The final output level from the ramp stage is
equal to the RCF Fine Scale output level multiplied by the last
ramp coefficient.
Figure 26. View of an unmodulated carrier with linear
ramp-down and ramp-up and rest time between ramps
set to 0.
Figure 27. View of an unmodulated carrier with linear
ramp-down and ramp-up and rest time between ramps
set to 30 (RCF output sample time periods)
Ramp Triggering
The ramp sequence is triggered by the Fine Scale Hold-Off
counter. The counter is loaded with a 16-bit user-specified value
(>1 and <2
16) upon receipt of a sync pulse. The counter then
counts-down (master CLK cycles) to 1, triggers the Ramp sequence
and updates the Fine Scale factor. The counter will then stop at
a count of zero. If the counter is initially loaded with 0, then the
scale hold-off counter is bypassed and will not trigger any
succeeding events. There are three ways to provide the sync pulse
that loads the hold-off counter that ultimately triggers the ramp:
1. Serial Input sync. This method is selected when “Serial Time
Slot Sync Enable”, 0xn16:2, is set to Logic 1 and appropriate
serial word input bits are set as described in Figure 17
(AD6623 Data Format and Bit Definition chart). This allows a
channel’s Fine Scale Hold-Off Counter to be loaded and a power
ramp sequence to be triggered by a data word without resorting
to hardware or software generated sync pulses. This sync signal is
routed to the OR gate following the Time Slot Sync multiplexer
shown in the Sync Control block diagram, Figure 37.
2. Hardware Sync. Sync Pins 0, 1, 2, and 3 provide a means to
load the fine scale hold-off counter using the channel’s “Time
Slot Sync” multiplexer. The multiplexer allows selection of
the desired hard or “pin”-sync signal using two software
controlled select lines at register addresses 0xn0F:17 and
0xn0F:16. Pin-Sync is the most precise method of synchro-
nization. This block shares 2 signals with the Beam Sync block.
They are Software Beam Sync and Sync0. This means that
whenever a Sync0 or soft beam sync is sent to the Beam Sync
block, the same signals are also sent to the Time Slot Sync block.
3. Software Sync. This function allows the user to load Start,
Hop, Beam and Fine Scale holdoff counters via software
commands through the AD6623 Microport. Sync signals
generated in this manner are the least precise means of
synchronization. All software sync bits are located at address
5 of the external register (see Table XXI External Registers).
The Time Slot soft-sync is derived from the shared Beam
Sync soft sync. Setting D6, “Beam”, high will generate a soft
sync signal that loads the Fine Scale hold-off counter as well
as the Beam Sync phase hold-off counter. User must select
which channel(s) will receive the soft sync signal(s) using bits
D0 through D3 at external address 5 and select what type of
sync signal(s) is to be generated (using bits D4, 5 and 6 at
address 5). As an example, to generate a Time Slot soft sync for
channel C, a user would set bits D2 and D6 high. D6 is the actual
sync signal and D2 routes the sync signal only to channel C.
Special Handling Required for SYNC0 Pin-Sync
Proper routing of Sync0 (a hardware sync pulse) for Time Slot
Sync may require bits in several registers to be set depending
upon the number of active channels. These control bits are
located in the Internal “Common Function” Registers (address
0x001) and the Internal “Channel Function” Registers (address
0xn00, 0xn03, 0xn05, 0xn0F). Address 0x001 contains 8 bits
that will mask the distribution of pin-sync pulses from Sync0 to
all channels and enable which sync multiplexers (start, hop, and
beam) receive Sync0 pulses. Furthermore, the MSB at 0x001 is
a “First Sync Only” flag that, when high, allows only one Sync0
pulse to be routed to the selected sync block(s). Following this,
all 8-bits of register 0x001 are cleared to completely mask off
subsequent pulses.
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