參數(shù)資料
型號： AD6623ASZ
廠商： Analog Devices Inc
文件頁數(shù)： 18/48頁
文件大小： 0K
描述： IC TSP 4CHAN 104MSPS 128MQFP
標(biāo)準(zhǔn)包裝： 1
應(yīng)用： 傳輸信息處理器
接口： 串行
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-MQFP（14x20）
包裝： 托盤
安裝類型： 表面貼裝
REV. A
AD6623
–25–
–150
–1
dB
01
2
–130
–110
–90
–70
–50
–30
–10
10
–3
–2
3
Figure 30. Filtered CIC5 Images
Table XII lists maximum bandwidth that will be rejected to various
levels for CIC5 interpolation factors from 1 to 32. The example
above corresponds to the listing in the –110 dB column and the
LCIC5 = 5 row. It is worth noting here that the rejection of the
CIC5 improves as the interpolation factor increases.
Table XII. Max Bandwidth of Rejection for LCIC5 Values
LCIC5
–110 dB
–100 dB
–90 dB
–80 dB
–70 dB
1
Full
2
0.101
0.127
0.160
0.203
0.256
3
0.126
0.159
0.198
0.246
0.307
4
0.136
0.170
0.211
0.262
0.325
5
0.136
0.175
0.217
0.269
0.333
6
0.143
0.178
0.220
0.282
0.337
7
0.144
0.179
0.222
0.275
0.340
8
0.145
0.180
0.224
0.276
0.341
9
0.146
0.181
0.224
0.277
0.342
10
0.146
0.182
0.225
0.278
0.343
11
0.147
0.182
0.226
0.278
0.344
12
0.147
0.182
0.226
0.279
0.344
13
0.147
0.183
0.226
0.279
0.345
14
0.147
0.183
0.226
0.279
0.345
15
0.148
0.183
0.227
0.280
0.345
16
0.148
0.183
0.227
0.280
0.345
17
0.148
0.183
0.227
0.280
0.346
18
0.148
0.183
0.227
0.280
0.346
19
0.148
0.183
0.227
0.280
0.346
20
0.148
0.184
0.227
0.280
0.346
21
0.148
0.184
0.227
0.280
0.346
22
0.148
0.184
0.227
0.280
0.346
23
0.148
0.184
0.227
0.280
0.346
24
0.148
0.184
0.227
0.280
0.346
25
0.148
0.184
0.227
0.281
0.346
26
0.148
0.184
0.227
0.281
0.346
27
0.148
0.184
0.227
0.281
0.346
28
0.148
0.184
0.227
0.281
0.346
29
0.148
0.184
0.227
0.281
0.346
30
0.148
0.184
0.227
0.281
0.346
31
0.148
0.184
0.227
0.281
0.346
32
0.148
0.184
0.228
0.281
0.346
THE rCIC2 RESAMPLING INTERPOLATION FILTER
The rCIC2 filter is a second order re-sampling Cascaded Inte-
grator Comb filter whose impulse response is defined by its
rate-change factors, LrCIC2 and MrCIC2. The rCIC2 filter is imple-
mented using a technique that does not require a faster clock
than the output rate thus simplifying design and saving power
while maintaining jitter-free operation. The rCIC2 stage allows
for noninteger relationships between the input data rate and the
master clock. This allows easier implementation of systems that
are either multimode or require a clock that is not a multiple of
the input data rate. The overall effect is referred to as “rate-
change”. A specific rate-change is accomplished by choosing
appropriate interpolation and decimation values for equation
(17) below. For example, if an interpolation ratio of 2.69 is
needed, then set LrCIC2 = 269 and MrCIC2 = 100.
Permissible
Values of L
rCIC2 and MrCIC2
The two parameters that determine the rate-change of the rCIC2
filter are:
1. The interpolation factor, LrCIC2, ranging from 1 to 4096 (12 bits)
2. The decimation factor, MrCIC2, ranging from 1 to 512 (9 bits)
The range of LrCIC2 is limited by LCIC5 according to Table XIII.
Table XIII. Maximum Permissible LrCIC2 Values
Chosen LCIC5 Value
Maximum Allowed LrCIC2 Value
1 to 22
4095
23
3836
24
3236
25
2748
26
2349
27
2020
28
1746
29
1518
30
1325
31
1162
32
1024
MrCIC2 is restricted by equations (17) and (18) below.
M
L
COMPLEX
rCIC
2
1
≤
+
(17)
Where: LrCIC2 = Interpolation of rCIC2
COMPLEX = Complex Output Mode (off = 0, on = 1),
() (
)
(
)
24
6
1
5
2
×+ ×
+ ≠ +
×
TPP
APE
COMPLEX
ceil L
L
M
CIC
rCIC
(18)
Where:
TPP = Taps Per Phase (of RAM Coefficient Filter)
APE = Allpass Phase Equalizer (off = 0, on = 1)
COMPLEX = Complex Output Mode (off = 0, on = 1)
ceil = when a value within the parenthesis is not an integer,
then round-up to the next integer (e.g., 9.001 = 10)
LCIC5 = Interpolation rate of CIC5
LrCIC2 = Interpolation of rCIC2
MrCIC2 = Decimation of rCIC2
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