
REV. A
AD6623
–37–
Channel Function Registers (continued)
Internal Address
Bit
AD6622 Compatible Description
AD6623 Extensions Description
0x105
17–16
Reserved
Ch. A Phase Sync Select
2
00: Sync0 (See 0x001 Beam)
01: Sync1
10: Sync2
11: Sync3
15–0
Ch. A NCO Phase Offset Update Hold–off Counter
2
No Change
0x106
7–5
Reserved
No Change
4–0
Ch. A CIC Scale, SCIC
No Change
0x107
8–0
Reserved
Ch. A CIC2 Decimation, M2 –1
0x108
11–8
Reserved
Ch. A CCI2 Interpolation, L2 –1, extended
7–0
Ch. A C1C2 Interpolation, L2 –1
No Change
0x109
7–0
Ch. A C1C5 Interpolation, L5 –1
No Change
0x10A
15–8
Reserved
Ch. A RCF TapsB, NRCF – 1 (8 bits)
2
7Reserved
Ch. A RCF TapsA, NRCF – 1 (new MSB)
3
6–0
Ch. A RCF TapsA, NRCF – 1 (7 bits)
2
No Change
3
0x10B
7
Reserved
Ch. A RCF Coef Offset, ORCF (new MSB)
3
6–0
Ch. A RCF Coefficient Offset, ORCF (7 bits)
2
No Change
3
0x10C
15–10
Unused
Reserved
9
Unused
Ch. A Compact FIR Input Word Length
0: 16 bits—8 I followed by 8 Q
1: 24 bits—12 I followed by 12 Q
8
Unused
Ch. A RCF PRBS Enable
7Ch. A PRBS Length
2
Ch. A RCF PRBS Length
2
0: 15
1: 8,388,607
6Ch. A RCF PRBS Enable
Ch. A RCF Mode Select (1 of 3)
3
5Ch. A RCF Mode Select (1 of 2)
2
Ch. A RCF Mode Select (2 of 3)
3
4Ch. A RCF Mode Select (2 of 2)
2
Ch. A RCF Mode Select (3 of 3)
3
00: FIR
000: FIR
01: FIR
001:
/4–DQPSK
10: QPSK
010: GMSK
11: MSK
011: MSK
100: FIR, Compact Input Resolution
101: 8–PSK
110: 3
π/8–8PSK
111: QPSK
3–0
Ch. A RCF (Taps per Phase) –1
2
No Change
3
0x10D
7–6
Ch. A RCF Coarse Scale (a)
No Change
3
00: 0 dB
01: –6 dB
10: –12 dB
11: –18 dB
5Ch. A RCF Phase EQ Enable
No Change
4–0
Ch. A Serial Clock Divisor (2, 4, …64)
Ch. A Serial Clock Divisor (1, 2,…32)
0x10E
15
Ch. A Serial Fine Scale Factor Enable
Ch. A Unsigned Scale Factor
3
This is extended to allow values in the
range (0–2).
14–2
Ch. A RCF Unsigned Scale Factor
3
No Change
3
1–0
Reserved
0x10F
17–16
Unused
Ch. A Time Slot Sync Select
00: Sync0 (See 0x001 Beam)
01: Sync1
10: Sync2
11: Sync3
15–0
Ch. A RCF Scale Hold–Off Counter
2
The counter is unchanged, but instead of
just scale update, when the counter hits one,
the following sequence is initiated:
1. Ramp Down (if Ramp is enabled)
2. Update RCF Mode Select registers
marked with “2”.
3. Ramp Up (if Ramp is enabled)