參數(shù)資料
型號(hào)： AD6623ASZ
廠商： Analog Devices Inc
文件頁數(shù)： 33/48頁
文件大?。?/td> 0K
描述： IC TSP 4CHAN 104MSPS 128MQFP
標(biāo)準(zhǔn)包裝： 1
應(yīng)用： 傳輸信息處理器
接口： 串行
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-MQFP（14x20）
包裝： 托盤
安裝類型： 表面貼裝
REV. A
AD6623
–39–
(27)
(0xn00) Start Update Hold-Off Counter
See the Synchronization section for detailed explanation. If no
synchronization is required, this register should be set to 0.
Bits 17–16: The Start Sync Select bits are used to set which
sync pin will initiate a start sequence.
Bits 15–0: The Start Update Hold-Off Counter is used to
synchronize start–up of AD6623 channels and can
be used to synchronize multiple chips. The Start
Update Hold-Off Counter is clocked by the AD6623
CLK (master clock).
(0xn01) NCO Control
Bit 1:0
Set the NCO scaling per Table XXII.
Table XXII. NCO Control (0xn01)
Bit 1
Bit 0
NCO Output Level
00
–6 dB (no attenuation)
01
–12 dB attenuation
10
–18 dB attenuation
11
–24 dB attenuation
Bit 2:
High clears the NCO phase accumulator to 0 on
either a Soft Sync or Pin Sync (see Synchronization
for details).
Bit 3:
High enables NCO phase dither.
Bit 4:
High enables NCO amplitude dither.
Bits 7–5:
Reserved and should be written low.
(0xn02) NCO Frequency
This register is a 32-bit unsigned integer that sets the NCO
Frequency. The NCO Frequency contains a shadow register for
synchronization purposes. The NCO frequency. can be read
back directly; however, the shadow register cannot.
NCO
f
CLK
FREQUENCY
CHANNEL
=×
2
32
NCO output frequency should not exceed approximately 45%
of the CLK.This makes allowance for the image filtering after
D/A conversion.
(0xn03) NCO Frequency Update Hold-Off Counter
See the Synchronization section for detailed explanation. If no
synchronization is required, this register should be set to 0.
Bits 17–16: The Hop Sync Select bits are used to set which sync
pin will initiate a hop sequence.
Bits 15–0: The Hold-Off Counter is used to synchronize the
change of NCO frequencies.
(0xn04) NCO Phase Offset
This register is a 16-bit unsigned integer that is added to the phase
accumulator of the NCO. This allows phase synchronization of
multiple channels of the AD6623(s). The NCO Phase Offset contains
a shadow register for synchronization purposes. The shadow can
be read back directly, the NCO Phase Offset cannot. See the
Synchronization section for details.
(0xn05) NCO Phase Offset Update Hold-Off Counter
See the Synchronization section for a detailed explanation. If no
synchronization is required, this register should be set to 0.
Bits 17–16: The Phase Sync Select bits are used to set which sync
pin will initiate a phase sync sequence.
Bits 15–0: The Hold-Off Counter is used to synchronize the
change of NCO phases.
(0xn06) CIC Scale
Bits 4–0: Sets the CIC scaling per the equation below.
CIC Scale
ceil
L
CIC
_
=×
×
()
log
25
4
2
(28)
See the CIC section for details.
(0xn07) CIC2 Decimation – 1 (MCIC2 – 1)
This register is used to set the decimation in the CIC2 filter. The
value written to this register is the decimation minus one. The
CIC2 decimation can range from 1 to 512 depending upon the
interpolation of the CIC2. There is no timing error associated
with this decimation. See the CIC2 section for further details.
(0xn08) CIC2 Interpolation – 1 (LCIC2 – 1)
This register is used to set the interpolation in the CIC2 filter.
The value written to this register is the interpolation minus one.
The CIC2 interpolation can range from 1 to 4096. LrCIC2 must
be chosen equal to or larger than MrCIC2 and both must be chosen
such that a suitable CIC2 Scalar can be chosen. For more details
the CIC2 section should be consulted.
(0xn09) CIC5 Interpolation – 1
This register sets the interpolation rate for the CIC5 filter stage
(unsigned integer). The programmed value is the CIC5 Interpo-
lation – 1. Maximum interpolation is limited by the CIC scaling
available (See the CIC section).
(0xn0A) Number of RCF Coefficients – 1
This register sets the number of RCF Coefficients and is limited
to a maximum of 256. The programmed value is the number of
RCF Coefficients – 1. There is an A register and a B register at
this memory location. Value A is used when the RCF is operating
in mode 0 and value B is used when in mode 1. The RCF mode
bit of interest here is bit 6 of address 0xn0C.
(0xn0B) RCF Coefficient Offset
This register sets the offset for RCF Coefficients and is normally
set to 0. It can be viewed as a pointer which selects the portion
of the CMEM used when computing the RCF filter. This allows
multiple filters to be stored in the Coefficient memory space, selecting
the appropriate filter by setting the offset.
(0xn0C) Channel Mode Control 1
Bit 9:
High, selecting compact FIR mode results in 24-bit
serial word length (12 I followed by 12 Q). When
low, selecting compact FIR mode results in 16-bit
serial word length (8 I followed by 8 Q).
Bit 8:
High enables RCF Pseudo-Random Input Select.
Bit 7:
High selects a Pseudo-Random sequence length of
8,388,607. Low selects a Pseudo-Random Sequence
length of 15.
Bits 6–4:
Sets the channel input format as shown in Table XXIII.
Table XXIII. Channel Inputs
Bit 6
Bit 5
Bit 4
Input Mode
000FIR
001
/4-DQPSK
010GSM
011MSK
100Compact FIR
101
8PSK
1103 /8-8PSK
111
QPSK
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