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參數(shù)資料
| 型號： | AD6623ASZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/48頁 |
| 文件大小： | 0K |
| 描述： | IC TSP 4CHAN 104MSPS 128MQFP |
| 標準包裝： | 1 |
| 應用： | 傳輸信息處理器 |
| 接口： | 串行 |
| 封裝/外殼： | 128-BFQFP |
| 供應商設備封裝： | 128-MQFP（14x20） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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REV. A
AD6623
–16–
See Table II for usable SCLK divider values and the corre-
sponding SCLK and fSCLK/fSDFO ratio for the example of L = 2560.
In conclusion, SDFO rate is determined by the AD6623 CLK
rate and the interpolation rate of the channel. The SDFO rate is
equal to the channel input rate. The channel interpolation is
equal to RCF interpolation times CIC5 interpolation, times
CIC2 interpolation:
LL
L
M
RCF
CIC
CRIC
=×
×
5
2
(4)
The SCLK divide ratio is determined by SCLKdivider as shown
in equation 3. The SCLK must be fast enough to input 32 bits
of data prior to the next SDFO. Extra SCLKs are ignored by
the serial port.
Table II. Example of Usable SCLK Divider
Values and fSCLK/fSDFO Ratios for L = 2560
SCLKdivider fSCLK/fSDFO
0
2560
1
1280
3
640
4
512
7
320
9
256
15
160
19
128
31
80
PROGRAMMABLE RAM COEFFICIENT FILTER (RCF)
Each channel has a fully independent RAM Coefficient Filter (RCF).
The RCF accepts data from the Serial Port, processes it, and
passes the resultant I and Q data to the CIC filter. A variety of
processing options may be selected individually or in combination,
including PSK and MSK modulation, FIR filtering, all-pass phase
equalization, and scaling with arbitrary ramping. See Table III.
Table III. Data Format Processing Options
Processing Block
Input Data
Output Data
Interpolating FIR Filter
I and Q
PSK Modulator
2 or 3 bits
per symbol
Unfiltered I
and Q:
/4-QPSK,
8-PSK, or
3 /8-8-PSK
MSK Modulator
1 bit per symbol
Filtered MSK
or GSM I and Q
QPSK
2 bits per symbol
Filtered QPSK
I and Q
All-pass Phase Equalizer
I and Q
Scale and Ramp
I and Q
Serial Data Format
The format of data applied to the serial port is determined by
the RCF mode selected in Control Register 0xn0C. Below is a
table showing the RCF modes and input data format that it sets.
Table I. Serial Data Format
0xn0C
Serial Data
RCF
Bit 6
Bit 5
Bit 4
Word Length
Mode
0
0032
FIR
00
1
/4-DQPSK
01
0
GMSK
01
1
MSK
1
00
24 (Bit 9 is high)
FIR,
16 (Bit 9 is low)
compact
10
1
8-PSK
11
0
3 /8-8-PSK
11
1
QPSK
The serial data input, SDIN, accepts 32-bit words as channel input
data. The 32-bit word is interpreted as two 16-bit two’s comple-
ment quadrature words, I followed by Q, MSB first. This results in
linear I and Q data being provided to the RCF. The first bit is
shifted into the serial port starting on the next rising edge of SCLK
after the SDFO pulse. Figure 16 shows a timing diagram for SCLK
master (SCS = 0) and SDFO set for frame request (SFE = 0).
tDSDFO0A
tHSDI0
SCLK
SDFO
SDI
DATAn
CLK
tSSDI0
CLKn
tSSDI0
Figure 16. Serial Port Switching Characteristics
As an example of the Serial Port operation, consider a CLK
frequency of 62.208 MHz and a channel interpolation of 2560. In
that case, the input sample rate is 24.3 kSPS (62.208 MHz/2560),
which is also the SDFO rate. Substituting, fSCLK
≥ 32 3 f
SDFO into
the equation and solving for SCLKdivider, we find the minimum
value for SCLKdivider according to the equation below.
SCLKdivider
f
CLK
SDFO
≤
×
32
(3)
Evaluating this equation for our example, SCLKdivider must be
less than or equal to 79. Since the SCLKdivider channel register is
a 5-bit unsigned number it can only range from 0 to 31. Any value
in that range will be valid for this example, but if it is important
that the SDFO period is constant, then there is another restric-
tion. For regular frames, the ratio fSCLK/fSDFO must be equal to
an integer of 32 or larger. For this example, constant SDFO
periods can only be achieved with an SCLK divider of 31 or less.
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