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參數(shù)資料
| 型號(hào)： | AD6623ASZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 44/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TSP 4CHAN 104MSPS 128MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 傳輸信息處理器 |
| 接口： | 串行 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-MQFP（14x20） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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REV. A
–5–
AD6623
GENERAL TIMING CHARACTERISTICS1, 2
Test
AD6623AS
Parameter (Conditions)
Temp
Level
Min
Typ
Max
Unit
CLK Timing Requirements:
tCLK
CLK Period
Full
I
9.6
ns
tCLKL
CLK Width Low
Full
IV
3
ns
tCLKH
CLK Width High
Full
IV
3
0.5
× tCLK
ns
RESET Timing Requirement:
tRESL
RESET Width Low
Full
I
30.0
ns
Input Data Timing Requirements:
tSI
INOUT[17:0], QIN to
↑CLK Setup Time
Full
IV
1
ns
tHI
INOUT[17:0], QIN to
↑CLK Hold Time
Full
IV
2
ns
Output Data Timing Characteristics:
tDO
↑CLK to OUT[17:0], INOUT[17:0],
QOUT Output Delay Time
Full
IV
2
6
ns
tDZO
OEN HIGH to OUT[17:0] Active
Full
IV
3
7.5
ns
SYNC Timing Requirements:
tSS
SYNC(0, 1, 2, 3) to
↑CLK Setup Time
Full
IV
1
ns
tHS
SYNC(0, 1, 2, 3) to
↑CLK Hold Time
Full
IV
2
ns
Master Mode Serial Port Timing Requirements (SCS = 0):
Switching Characteristics
3
tDSCLK1
↑CLK to ↑SCLK Delay (divide by 1)
Full
IV
4
10.5
ns
tDSCLKH
↑CLK to ↑SCLK Delay (for any other divisor) Full
IV
5
13
ns
tDSCLKL
↑CLK to ↓SCLK Delay
(divide by 2 or even number)
Full
IV
3.5
9
ns
tDSCLKLL
↓CLK to ↓SCLK Delay
(divide by 3 or odd number)
Full
IV
4
10
ns
Channel is Self-Framing
tSSDI0
SDIN to
↑SCLK Setup Time
Full
IV
1.7
ns
tHSDI0
SDIN to
↑SCLK Hold Time
Full
IV
0
ns
tDSFO0A
↑SCLK to SDFO Delay
Full
IV
0.5
3.5
ns
Channel is External-Framing
tSSFI0
SDFI to
↑SCLK Setup Time
Full
IV
2
ns
tHSFI0
SDFI to
↑SCLK Hold Time
Full
IV
0
ns
tSSDI0
SDIN to
↑SCLK Setup Time
Full
IV
2
ns
tHSDI0
SDIN to
↑SCLK Hold Time
Full
IV
0
ns
tDSFO0B
↑SCLK to SDFO Delay
Full
IV
0.5
3
ns
Slave Mode Serial Port Timing Requirements (SCS = 1):
Switching Characteristics
3
tSCLK
SCLK Period
Full
IV
2
tCLK
ns
tSCLKL
SCLK Low Time
Full
IV
3.5
ns
tSCLKH
SCLK High Time
Full
IV
3.5
ns
Channel is Self-Framing
tSSDH
SDIN to
↑SCLK Setup Time
Full
IV
1
ns
tHSDH
SDIN to
↑SCLK Hold Time
Full
IV
2.5
ns
tDSFO1
↑SCLK to SDFO Delay
Full
IV
4
10
ns
Channel is External-Framing
tSSFI1
SDFI to
↑SCLK Setup Time
Full
IV
2
ns
tHSFI1
SDFI to
↑SCLK Hold Time
Full
IV
1
ns
tSSDI1
SDIN to
↑SCLK Setup Time
Full
IV
1
ns
tHSDI1
SDIN to
↑SCLK Hold Time
Full
IV
2.5
ns
tDSFO1
↓SCLK to SDFO Delay
Full
IV
10
ns
NOTES
1All Timing Specifications valid over VDD range of 2.375 V to 2.675 V and VDDIO range of 3.0 V to 3.6 V.
2C
LOAD = 40 pF on all outputs (unless otherwise specified).
3The timing parameters for SCLK, SDIN, SDFI, SDFO, and SYNC apply to all four channels (A, B, C, and D).
Specifications subject to change without notice.
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