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參數(shù)資料
| 型號： | AD6623ASZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TSP 4CHAN 104MSPS 128MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 傳輸信息處理器 |
| 接口： | 串行 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-MQFP（14x20） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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REV. A
AD6623
–22–
Table X. Coefficient Weights
Register Value
Coefficient Weight
0x7FFF
+1.999938964844
..
0x0001
+0.00006103515625
0x0000
0
0xFFFF
–0.00006103515625
..
0x8001
–1.999938964844
0x8000
–2
Table XI shows the recommended b1 and b2 coefficients for the
respective oversampling rate.
Table XI. b1 and b2 Coefficients
Over-
sampling
b0
b1
b2
11
–0.25421 (0.efbbh)
+0.11188 (0.0729h)
21
–0.96075 (0.c283h)
+0.33447 (0.1568h)
31
–1.28210 (0.adf2h)
+0.48181 (0.1ed6h)
41
–1.45514 (0.a2dfh)
+0.57831 (0.2503h)
51
–1.56195 (0.9c09h)
+0.64526 (0.294ch)
61
–1.63409 (0.976bh)
+0.69415 (0.2c6dh)
71
–1.68604 (0.9418h)
+0.73132 (0.2eceh)
81
–1.72516 (0.9197h)
+0.76050 (0.30ach)
FINE SCALE AND POWER RAMP
Fine Scale multiplier factors in the range [0, 2) with a step resolution
of 2
–16. Power Ramp multiplier factors in the range [0, 1) with a
step resolution of 2
–14.
FINE SCALING
Fine Scale multiplier factors range from [0, 2) with a step resolution
of 2
–15 in the AD6622 emulation mode and 2–16 in the AD6623
emulation mode. Scaling values for each channel are pro-
grammed at register 0xn0E in the AD6623 internal memory
using the Microport interface.
RCF POWER RAMPING
When the output of the AD6623 is programmed to be a rapid
series of on/off bursts of data, the DAC used to produce an
analog output signal will produce undesirable spectral components
that should (or must) be suppressed. Shaping or “ramping” the
transition from no power to full power, and vice versa, reduces
the amplitude of these spurious signals. To program the ramp
function a user must provide, through the Microport, the
ramp memory (RMEM) coefficient values (up to 64), number
of RMEM coefficients to “construct” the ramp (1 to 64) and
selection of a synchronizing signal source as discussed below.
The programmable power ramp up/down unit allows power
ramping on time-slot basis as specified for some wireless
transmission technologies (e.g. TDMA).
The shape of the ramp is stored in RAM. The RAM coefficients
(RMEM) allow complete sample-by-sample control at the RCF
interpolated rate. This is particularly useful for time division
multiplexed standards such as GSM/EDGE. A time slot or
“burst” is ramped-up and down by multiplying the Fine Scaled
output of the RCF by a series of up to 64 ramp coefficients. If more
ramp resolution is required, up to 64 interpolated coefficients
can be added if the Ramp Interpolation bit, 0xn16:1, is set to
SERIAL
8-PSK
MAPPER
SPH
[2:0]
[3:0]
PHASE
[3:0]
RPH
3
Figure 24. 3
π/8-8-PSK Mapper
MSK Look-Up Table
The MSK Look-Up Table mode for the RCF is selected in Control
Register 0xn0C. In the MSK Mode, the RCF performs arbitrary
pulse-shaping based on four symbols of impulse response. For the
MSK Mode, the serial input format is 1 bit of data.
GMSK Look-Up Table
The GMSK Look-Up Table mode for the RCF is selected in Control
Register 0xn0C. In the GMSK Mode, the RCF performs arbitrary
pulse-shaping based on four symbols of impulse response. For the
GMSK Mode, the serial input format is 1 Bit of data.
QPSK Look-Up Table
The QPSK Filter mode for the RCF is selected in Control
Register 0xn0C. In the QPSK Mode, the RCF performs baseband
linear pulse-shaping based on filter impulse response up to 12
symbols. For the QPSK Mode, the serial input format is 1 Bit I
followed by 1 Bit Q.
PHASE EQUALIZER
The IS-95 Standard includes a phase equalizer after matched
filtering at the baseband transmit side of a base station. This
filter pre-distorts the transmitted signal at the base station in
order to compensate for the distortion introduced to the received
signal by the analog baseband filtering in a handset. The AD6623
includes this functionality in the form of an Infinite Impulse
Response (IIR) all-pass filter in the RCF. This Phase Equalizer
pre-distort filter has the following transfer function:
Hz
Yz
Xz
bz
b z
zb z
b
()
== ++
++
11
2
12
2
(9)
Z–1
X(z)
Y(z)
b2
b1
Figure 25. Second Order All-Pass IIR Filter
The Allpass Phase Equalizer (APE) is enabled (logic 1) or disabled
(logic 0) in Control Register 0xn0D:5. The value of Bit 5 then
becomes the value of the APE term in Equation 7. The coefficients
b1 and b2 are located in Control Registers 0xn10 and 0xn11
respectively.
The format for b1 and b2 is two’s complement fractional binary
with a range of [–2, 2). With one bit for sign at most significant bit
position there are 15 bits for magnitude. The value of one bit is
(2
–15)
× 2, or 0.00006103515625. The register values, in hexadecimal,
and the corresponding coefficient weight from positive full-scale
through zero to negative full-scale is illustrated in Table X.
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