參數(shù)資料
型號(hào)： AD6623ASZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 4/48頁(yè)
文件大?。?/td> 0K
描述： IC TSP 4CHAN 104MSPS 128MQFP
標(biāo)準(zhǔn)包裝： 1
應(yīng)用： 傳輸信息處理器
接口： 串行
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-MQFP（14x20）
包裝： 托盤
安裝類型： 表面貼裝
REV. A
AD6623
–12–
128-LEAD FUNCTION DESCRIPTIONS
Pin Number
Mnemonic
Type
Description
1, 3–5, 9, 19–21, 31, 32, 34–36, 38, 39,
GND
P
Ground Connection
42, 52–54, 64–65, 68, 72, 83–85, 95, 96,
98, 99, 102, 103, 116, 128
2
OEN
1
IActive High Output Enable Pin
29, 28, 27, 25, 24, 23, 22, 18, 17, 16, 15,
OUT[17:0]
O/T
Parallel Output Data
13, 12, 11, 10, 8, 7, 6
47, 59, 66, 104, 127
VDD
P
2.5 V Supply
14, 26, 41, 78, 90, 110, 122
VDDIO
P
3.3 V Supply
30
QOUT
O/T
When HIGH indicates Q Output Data (Complex Output Mode)
33, 37, 40, 43, 44, 45, 46, 48
D[7:0]
I/O/T
Bidirectional Microport Data
49
DS (RD)I
INM Mode: Read Signal, MNM Mode: Data Strobe Signal
50
DTACK (RDY) O
Acknowledgment of a Completed Transaction (Signals when
P Port Is Ready for an Access) Open Drain, Must Be
Pulled Up Externally
51
RW (
WR)I
Active HIGH Read, Active Low Write
55
MODE
I
Sets Microport Mode: MODE = 1, MNM Mode;
MODE = 0, INM Mode
56, 57, 58
A[2:0]
I
Microport Address Bus
60
CS
IChip Select, Active low enable for
P Access
61
RESET2
IActive Low Reset Pin
62
SYNC0
1
ISYNC Signal for Synchronizing Multiple AD6623s
63
SYNC1
1
ISYNC Signal for Synchronizing Multiple AD6623s
67
CLK
1
I
Input Clock
69
SYNC2
1
ISYNC Signal for Synchronizing Multiple AD6623s
70
QIN
1
I
When HIGH indicates Q input data (Complex Input Mode)
71, 74–77, 79–82, 86–89, 91–94, 97
INOUT[17:0]
1
I/O
Wideband Input/Output Data (Allows Cascade of Multiple
AD6623 Chips In a System)
73
SYNC3
1
ISYNC Signal for Synchronizing Multiple AD6623s
100
TRST2
ITest Reset Pin
101
TCK
1
ITest Clock Input
105
SDFIA
I
Serial Data Frame Input—Channel A
106
TMS
2
ITest Mode Select
107
TDO
O
Test Data Output
108
TDI
1
ITest Data Input
109
SCLKA
I/O
Bidirectional Serial Clock—Channel A
111
SDFOA
O
Serial Data Frame Sync Output—Channel A
112
SDINA
1
I
Serial Data Input—Channel A
113
SCLKB
I/O
Bidirectional Serial Clock—Channel B
114
SDFOB
O
Serial Data Frame Sync Output—Channel B
115
SDFIB
I
Serial Data Frame Input —Channel B
117
SDFIC
I
Serial Data Frame Input—Channel C
118
SDINB
1
I
Serial Data Input—Channel B
119
SCLKC
I/O
Bidirectional Serial Clock—Channel C
120
SDFOC
O
Serial Data Frame Sync Output—Channel C
121
SDINC
1
I
Serial Data Input—Channel C
123
SCLKD
I/O
Bidirectional Serial Clock—Channel D
124
SDFOD
O
Serial Data Frame Sync Output—Channel D
125
SDIND
1
I
Serial Data Input—Channel D
126
SDFID
I
Serial Data Frame Input—Channel D
NOTES
1Pins with a Pull-Down resistor of nominal 70 k
.
2Pins with a Pull-Up resistor of nominal 70 k
.
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