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參數(shù)資料
| 型號(hào)： | AD6623ASZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TSP 4CHAN 104MSPS 128MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 傳輸信息處理器 |
| 接口： | 串行 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-MQFP（14x20） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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REV. A
AD6623
–18–
Table IV. FIR Filter Internal Precision
Minimum
Maximum
Signal
x
y Notation
Decimal
Hexadecimal (h)
Decimal
Hexadecimal (h)
I and Q Inputs
1.15
–1.00000
+1.00000
0.999969
0.FFFE
Coefficients
1.15
–1.00000
+1.00000
0.999969
0.FFFE
Product
2.18
–0.99969
+3.00020
1.000000
1.00000
Sum
4.18
–7.00000
+8.00000
7.999996
7.FFFFC
FIR Output
1.17
–1.00000
+1.00000
0.999992
0.FFFF8
INTERPOLATING
FIR
FILTER
INTERPOLATING
MSK
MODULATOR
INTERPOLATING
QPSK
MODULATOR
ALLPASS
PHASE
EQUALIZER
PSK
MODULATOR
SCALE
AND
RAMP
DATA FROM SERIAL PORT
DATA TO CIC FILTERS
Figure 18. RCF Block Diagram
The Scale and Ramp block adjusts the final magnitude of the
modulated RCF output. A synchronization pulse from the
SYNC0–3 pins or serial words can be used to command this
block to ramp down, pause, and ramp up to a new scale factor.
The shape of the ramp is stored in RAM, allowing complete
sample by sample control at the RCF interpolated rate. This is
particularly useful for time division multiplexed standards such
as GSM/EDGE. Modulator configurations can be updated
while the ramp is quiet, allowing for GSM and EDGE timeslots
to be multiplexed together without resetting or reconfiguring the
channel. Each of the RCF processing blocks is discussed in
greater detail in the following sections.
INTERPOLATING FIR FILTER
The Interpolating FIR Filter realizes a real, sum-of-products filter
on I and Q inputs using a single interleaved Multiply-Accumulator
(MAC) running at the CLK rate. The input signal is interpolated
by integer factors to produce arbitrary impulse responses up to
256 output samples long.
Each bus in the data path carries bipolar two’s complement values.
For the purpose of discussion, we will arbitrarily consider the radix
point positioned so that the input data ranges from –1 to just
below 1. In Figure 19, the data buses are marked x
× y to denote
finite precision limitations. A bus marked x
× y has x bits above
the radix and y bits below the radix, which implies a range from
–2
x–1 to 2x–1 – 2–y in 2–y steps. The range limits are tabulated in
Table IV for each bus. The hexadecimal values are bit-exact and
each MSB has negative weight. Note that the Product bus range is
limited by result of the multiplication and the two most significant
bits are the same except in one case.
DMEM
32 16
CMEM
256 16
INPUT
ACCUMULATOR
PRODUCT
4.18
1.15
INPUT
1.15
COEF
1.15
2.18
1.17
OUTPUT
20, 2–1, 2–2, OR 2–3
Figure 19. Interpolating FIR Filter Block Diagram
The RCF realizes a FIR filter with optional interpolation. The
FIR filter can produce impulse responses up to 256 output
samples long. The FIR response may be interpolated up to a
factor of 256, although the best filter performance is usually
achieved when the RCF interpolation factor (LRCF) is confined
to eight or below. The 256
× 16 coefficient memory (CMEM)
can be divided among an arbitrary number of filters, one of
which is selected by the Coefficient Offset Pointer (channel
address 0x0B). The polyphase implementation is an efficient
equivalent to an integer up-sampler followed FIR filter running
at the interpolated rate.
The AD6623 RCF realizes a sum-of-products filter using a
polyphase implementation. This mode is equivalent to an inter-
polator followed by a FIR filter running at the interpolated rate.
In the functional diagram below, the interpolating block in-
creases the rate by the RCF interpolation factor (LRCF) by inserting
LRCF–1 zero valued samples between every input sample. The next
block is a filter with a finite impulse response length (NRCF) and
an impulse response of h[n], where n is an integer from 0 to NRCF–1.
The difference equation for Figure 20 is written below, where
h[n] is the RCF impulse response, b[n] is the interpolated input
sample sequence at point ‘b’ in the diagram above, and c[n] is
the output sample sequence at point ‘c’ in Figure 20.
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