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參數(shù)資料
| 型號： | AD6623ASZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/48頁 |
| 文件大小： | 0K |
| 描述： | IC TSP 4CHAN 104MSPS 128MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 傳輸信息處理器 |
| 接口： | 串行 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-MQFP（14x20） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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REV. A
AD6623
–31–
Beam
A change in phase for a particular channel and can be synchronized
with respect to other channels or AD6623s. This change in phase
can be synchronized via microprocessor control or an external
Sync signal.
To set the amplitude without synchronization the following
method should be used.
Set Phase No Beam
1. Set the NCO Phase Offset Update Hold-Off Counter (0xn05)
to 0.
2. Load the appropriate NCO Phase Offset (0xn04). The NCO
Phase Offset will be immediately loaded.
Beam with SoftSync
The AD6623 includes the ability to synchronize a change in NCO
phase of multiple channels or chips under microprocessor control.
The NCO Phase Offset Update Hold-Off Counter in conjunction
with the Beam bit and the Sync bit (Ext Address 5) allow this
synchronization. Basically the NCO Phase Offset Update Hold-Off
Counter delays the new phase from being loaded into the NCO/RCF
by its value (number of AD6623 CLKs). The following method is
used to synchronize a beam in phase of multiple channels via
microprocessor control.
1. Write the NCO Phase Offset Update Hold-Off Counter (0xn05)
to the appropriate value (greater than 1 and less then 2
16–1).
2. Write the NCO Phase Offset register(s) to the new desired
phase and amplitude.
3. Write the Beam bit and the Sync(s) bit high (Ext Address 5).
4. This starts the NCO Phase Offset Update Hold-Off Counter
counting down. The counter is clocked with the AD6623
CLK signal. When it reaches a count of one the new phase is
loaded into the NCO.
Beam with Pin Sync
Four hardware sync pins are available on the AD6623 to provide
the most accurate synchronization, especially between multiple
AD6623s. Synchronization of beaming to a new NCO Phase
Offset with an external signal is accomplished using the
following method.
1. Write the NCO Phase Offset Hold-Off (0xn05) Counter(s)
to the appropriate value (greater than 1 and less than 2
16–1).
2. Write the NCO Phase Offset register(s) to the new desired
phase and amplitude.
3. Set the Beam on Pin Sync bit and the appropriate Sync Pin
Enable high (0xn01).
4. When the Sync pin is sampled high by the AD6623 CLK this
enables the count down of the NCO Phase Offset Hold-Off
counter. The counter is clocked with the AD6623 CLK signal.
When it reaches a count of one the new phase is loaded into
the NCO registers.
Time Slot (Ramp)
This enables power ramping and allows input data format
changes during the “quiet” period after ramp-down. It must be
synchronized using the Microport (soft sync), input data or a
hardware sync pin. A Time Slot normally takes the form of:
ramp-down to minimum power, “rest” period and ramp-up to
maximum output power. See the “RCF POWER RAMPING”
section of this data sheet for related information.
The PROG Mode bits located at External Address 4:7-4,
referred to below, must be set HIGH whenever RMEM (ramp
memory), CMEM (coefficient memory) or DMEM (data
memory) are to be programmed. However, when programming is
completed, the PROG bit for the channel(s) must be returned
LOW for proper channel functioning.
Set Output Power, No Ramp
The steps below assume that the user has established a data flow
from input to output of the AD6623.
1. Place the channel(s) in SLEEP Mode (external address 4:3-0,
write bit(s) high).
2. Set bit 0 of Internal Address 0xn16 (the channel’s Ramp
Enable bit) to Logic 0. This defeats the ramp function.
3. Set the fine scaling and coarse scaling control register values
associated with the RCF (0xn0D:7-6 and 0xn0E:15-2), CIC
(0xn06:4-0), NCO (0xn01:1-0) and SUMMATION stages to
the desired levels according to the SCALING section of this
data sheet.
4. Finally, re-establish an output data flow to a DAC by bringing
the appropriate SLEEP bits low and verify desired signal ampli-
tude. Note: a START sync pulse is automatically generated
when the channel is brought out of SLEEP Mode. The START
pulse loads the updated control register data to the appropriate
active counters and shadow registers.
Time Slot (Ramp) with SoftSync
Time Slot or ramping functions for each channel can be engaged
with software synchronizing words received through the Micro-
port. The RCF Fine Scale Hold-Off Counter in conjunction
with the Beam bit
* (which is the sync signal) and SyncA, B, C,
and/or D (the channel to be sync’ed) in External Register address
5 allow this synchronization. The RCF Fine Scale Hold-Off
Counter delays the beginning of the Time Slot function as well
as updating the Fine Scale amplitude value (if applicable). The
amount of time delay is set by the value (number of AD6623
CLK periods) written to the register at 0xn0F:15-0. Since the
Time Slot event is of short duration, the user should consider a
digital scope set for Normal or One-Shot triggering to capture
the event and verify functionality. The following steps are used
to synchronize a Time Slot or Ramp event with a software word
received through the Microport; they assume that the user has
established a data flow from input to output of the AD6623.
1. Place the channel(s) in SLEEP Mode (external address 4:3-0,
write bit(s) high) and in the PROG Mode (external address
4:7-4, write the bit(s) high).
2. Write the Fine Scale Hold-Off Counter (0xn0F:15-0) to the
appropriate value (>1 and <2
16–1).
3. Set the Ramp Enable bit (0xn16:0) high.
4. Load RMEM (ramp memory) with up to 64 coefficients
(0xn40-17F) with the desired values ranging from 0 to 2
14–1
that represent the “shape” of the ramp transition. Where 0 is
zero gain and 2
14–1 is unity gain.
5. Load the channel’s ramp length minus 1, up to 63 at 0xn17
6. Load the channel’s ramp rest time minus 1, up to 31, at 0xn19.
7. Re-establish an output data flow to the DAC by bringing the
channel(s) SLEEP bits low and PROG bits LOW.
8. Write the Beam bit
* high and desired Sync(A, B, C, and/or D)
bit(s) high at Ext. Address 5. Return Beam bit to Logic 0.
*The “Beam” soft sync signal is also routed to the Time Slot function. This is a
“shared” bit and it provides soft sync pulses to both the Phase Hold-Off and Fine
Scale Hold-Off counters simultaneously.
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