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參數(shù)資料
| 型號(hào)： | AD6623ASZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TSP 4CHAN 104MSPS 128MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 傳輸信息處理器 |
| 接口： | 串行 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-MQFP（14x20） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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REV. A
AD6623
–36–
Common Function Registers (not associated with a particular channel)
Internal Address
Bit
AD6622 Compatible Description
AD6623 Extensions Description
0x000
7
AD6623 Extension = 0
1
AD6623 Extension = 1
1
6–5
Reserved
No Change
4Reserved
Wideband Input Disable
1
3Reserved
Dual Output Enable
1
2Reserved
No Change
1Offset Binary Outputs
1
No Change
0Clip Wideband I/O
1
No Change
0x001
7
First Sync Only
2
No Change
6Beam on Pin Sync
2
No Change
5Hop on Pin Sync
2
No Change
4
Start on Pin Sync
2
No Change
3Ch. D Sync0 Pin Enable
2
No Change
2Ch. C Sync0 Pin Enable
2
No Change
1Ch. B Sync0 Pin Enable
2
No Change
0Ch. A Sync0 Pin Enable
2
No Change
0x002
23–0
Unused
BIST Counter
1, 2
0x003
15–0
Unused
BIST Value (read only)
Channel Function Registers (0x1xx = Ch. A, 0x2xx = Ch. B, 0x3xx = Ch. C, 0x4xx = Ch. D)
Internal Address
Bit
AD6622 Compatible Description
AD6623 Extensions Description
0x100
17–16
Unused
Ch. A Start Sync Select
2
00: Sync0 (See 0x001)
01: Sync1
10: Sync2
11: Sync3
15–0
Ch. A Start Hold-Off Counter
2
No Change
0x101
7–5
Reserved
No Change
4Ch. A NCO Amplitude Dither Enable
No Change
3Ch. A NCO Phase Dither Enable
No Change
2Ch. A NCO Clear Phase Accumulator on Sync
No Change
1–0
Ch. A NCO Scale
No Change
00: –6 dB
No Change
01: –12 dB
No Change
10: –18 dB
No Change
11: –24 dB
No Change
0x102
31–0
Ch. A NCO Frequency Value
2
No Change
0x103
17–16
Unused
Ch. A Hop Sync Select
2
00: Sync0 (See 0x001 Hop)
01: Sync1
10: Sync2
11: Sync3
15–0
Ch. A NCO Frequency Update Hold–Off Counter
2
No Change
0x104
15–0
Ch. A NCO Phase Offset
3
No Change
3
External Address 4 Sleep
Bits in this register determine how the chip is programmed and
enables the channels. The program bits (D7:D4) must be set high
to allow programming of CMEM and DMEM for each channel.
Sleep bits (D3:D0) are used to activate or sleep channels. These
can be used manually by the user to bring up a channel by simply
writing the required channel high. These bits can also be used in
conjunction with the Start and Sync signals available in External
Address 5 to synchronize the channels. See the Synchronization
section for a detailed explanation of different modes.
External Address 3:0 (Data Bytes)
These registers return or accept the data to be accessed for a
read or write to internal addresses.
INTERNAL COUNTER REGISTERS AND ON-CHIP RAM
AD6623 and AD6622 Compatibility
The AD6623 functions and programmability significantly exceed
those of the AD6622 while maintaining AD6622 pin compatibil-
ity and functionality when desired. AD6622 compatibility is selected
when Bit 7 of Internal Control Register 0x000 is low. In this state,
all AD6623 extended control registers are cleared. While in the
AD6622 mode the unused AD6623 pins are three-stated.
Listed below is the mapping of internal AD6623 registers.
AD6622 compatibility is selected by setting 0x000:7 low. In this
state, all AD6623 extended control registers are cleared. Registers
marked as “Reserved” must be written low.
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